SLAS646C December   2009  – May 2015 DAC3282

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC Specifications
    6. 6.6 Electrical Characteristics - AC Specifications
    7. 6.7 Electrical Characteristics - Digital Specifications
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input FIFO
      2. 7.3.2  FIFO Alarms
      3. 7.3.3  FIFO Modes of Operation
      4. 7.3.4  Dual Sync Sources Mode
      5. 7.3.5  Single Sync Source Mode
      6. 7.3.6  Bypass Mode
      7. 7.3.7  Data Pattern Checker
      8. 7.3.8  FIR Filters
      9. 7.3.9  Coarse Mixer
      10. 7.3.10 Digital Offset Control
      11. 7.3.11 Temperature Sensor
      12. 7.3.12 Sleep Modes
      13. 7.3.13 Reference Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Data Interface
      2. 7.4.2 LVPECL Inputs
      3. 7.4.3 LVDS Inputs
      4. 7.4.4 CMOS Digital Inputs
      5. 7.4.5 DAC Transfer Function
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CONFIG0 (address = 0x00) [reset = 0x70]
      2. 7.6.2  CONFIG1 (address = 0x01) [reset = 0x11]
      3. 7.6.3  CONFIG2 (address = 0x02) [reset = 0x00]
      4. 7.6.4  CONFIG3 (address = 0x03) [reset = 0x10]
      5. 7.6.5  CONFIG4 (address = 0x04) [reset = 0xFF]
      6. 7.6.6  CONFIG5 (address = 0x05) READ ONLY
      7. 7.6.7  CONFIG6 (address =0x06) [reset = 0x00]
      8. 7.6.8  CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
      9. 7.6.9  CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
      10. 7.6.10 CONFIG9 (address = 0x09) [reset = 0x7A]
      11. 7.6.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
      12. 7.6.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
      13. 7.6.13 CONFIG12 (address =0x0C) [reset = 0x45]
      14. 7.6.14 CONFIG13 (address =0x0D) [reset = 0x1A]
      15. 7.6.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
      16. 7.6.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
      17. 7.6.17 CONFIG16 (address = 0x10) [reset = 0xC6]
      18. 7.6.18 CONFIG17 (address = 0x11) [reset = 0x00]
      19. 7.6.19 CONFIG18 (address = 0x12) [reset = 0x02]
      20. 7.6.20 CONFIG19 (address = 0x13) [reset = 0x00]
      21. 7.6.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
      22. 7.6.22 CONFIG21 (address = 0x15) [reset = 0x00]
      23. 7.6.23 CONFIG22 (address = 0x16) [reset = 0x00]
      24. 7.6.24 CONFIG23 (address = 0x17) [reset = 0x00]
      25. 7.6.25 CONFIG24 (address = 0x18) [reset = 0x83]
      26. 7.6.26 CONFIG25 (address = 0x19) [reset = 0x00]
      27. 7.6.27 CONFIG26 (address = 0x1A) [reset = 0x00]
      28. 7.6.28 CONFIG27 (address =0x1B) [reset = 0x00]
      29. 7.6.29 CONFIG28 (address = 0x1C) [reset = 0x00]
      30. 7.6.30 CONFIG29 (address = 0x1D) [reset = 0x00]
      31. 7.6.31 CONFIG30 (address = 0x1E) [reset = 0x00]
      32. 7.6.32 VERSION31 (address = 0x1F) [reset = 0x43] (READ ONLY)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multi-device Synchronization
        1. 8.1.1.1 Multi-device Synchronization: Dual Sync Sources Mode
        2. 8.1.1.2 Multi-device Operation: Single Sync Source Mode
      2. 8.1.2 Analog Current Outputs
      3. 8.1.3 Passive Interface to Analog Quadrature Modulators
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-up Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Definition Of Specifications
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Dual, 16-Bit, 625 MSPS DACs
  • 8-Bit Input LVDS Data Bus
    • Byte-Wide Interleaved Data Load
    • 8 Sample Input FIFO
    • Optional Data Pattern Checker
  • Multi-DAC Synchronization
  • Optional 2x Interpolation Filter
  • Zero-IF Sinc Correction Filter
  • Fs/2 and ± Fs/4 Coarse Mixer
  • Digital Offset Adjustment for LO Correction
  • Temperature Sensor
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V reference
  • Differential Scalable Output: 2 to 20 mA
  • Low Power: 950 mW at 625 MSPS, 845 mW at 500 MHz, Full Operating Conditions
  • Space Saving Package: 48-pin 7×7mm VQFN

2 Applications

  • Cellular Base Stations
  • Diversity Transmit
  • Wideband Communications
  • Digital Synthesis

3 Description

The DAC3282 is a dual-channel 16-bit 625 MSPS digital-to-analog converter (DAC) with an 8-bit LVDS input data bus with on-chip termination, optional 2x interpolation filter, and internal voltage reference. The DAC3282 offers superior linearity, noise and crosstalk performance.

Input data can be interpolated by 2x through an on-chip interpolating FIR filter with over 85 dB of stop-band attenuation. Multiple DAC3282 devices can be fully synchronized.

The DAC3282 allows either a complex or real output. An optional coarse mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. The digital offset correction feature allows optimization of LO feed-through of an external quadrature modulator performing the final single sideband RF up- conversion.

The DAC3282 is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 48-pin 7×7mm VQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC3282 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DAC3282 fbd3_las646.gif