The DAC34H84 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS.
The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement.
A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of very high bandwidth signals. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12x12mm, 0.8mm pitch BGA package.
The DAC34H84 very low power, high bandwidth support, superior crosstalk, high dynamic range and features are an ideal fit for next generation communication systems.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC34H84 | NFBGA (196) | 12.00 mm x 12.00 mm |
Changes from C Revision (August 2012) to D Revision
Changes from B Revision (August 2011) to C Revision
Changes from A Revision (June 2011) to B Revision
Changes from * Revision (March 2011) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range(2) | DACVDD, DIGVDD, CLKVDD | –0.5 | 1.5 | V |
VFUSE | –0.5 | 1.5 | V | |
IOVDD, IOVDD2 | –0.5 | 4 | V | |
AVDD, PLLAVDD | –0.5 | 4 | V | |
Pin voltage range(2) | DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N, SYNCP/N | –0.5 | IOVDD + 0.5 | V |
DACCLKP/N, OSTRP/N | –0.5 | CLKVDD + 0.5 | V | |
ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, TXENA | –0.5 | IOVDD2 + 0.5 | V | |
IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N | –1.0 | AVDD + 0.5 | V | |
EXTIO, BIASJ | –0.5 | AVDD + 0.5 | V | |
LPF | –0.5 | PLLAVDD + 0.5 | V | |
Peak input current (any input) | 20 | mA | ||
Peak total input current (all inputs) | –30 | mA | ||
Operating free-air temperature range, TA: DAC34H84 | –40 | 85 | °C | |
Absolute maximum junction temperature, TJ | 150 | °C | ||
Storage temperature range, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
TJ | Recommended operating junction temperature | 105 | °C | ||
Maximum rated operating junction temperature(1) | 125 | ||||
TA | Recommended free-air temperature | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | DAC34H84 | UNIT | |
---|---|---|---|
ZAY (NFBGA) | |||
196 BALLS | |||
RθJA | Junction-to-ambient thermal resistance | 37.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 6.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 16.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Resolution | 16 | Bits | ||||
DC ACCURACY | ||||||
DNL | Differential nonlinearity | 1 LSB = IOUTFS/216 | ±2 | LSB | ||
INL | Integral nonlinearity | ±4 | LSB | |||
ANALOG OUTPUT | ||||||
Coarse gain linearity | ±0.04 | LSB | ||||
Offset error | Mid code offset | ±0.001 | %FSR | |||
Gain error | With external reference | ±2 | %FSR | |||
With internal reference | ±2 | %FSR | ||||
Gain mismatch | With internal reference | ±2 | %FSR | |||
Full scale output current | 10 | 20 | 30 | mA | ||
Output compliance range | –0.5 | 0.6 | V | |||
Output resistance | 300 | kΩ | ||||
Output capacitance | 5 | pF | ||||
REFERENCE OUTPUT | ||||||
VREF | Reference output voltage | 1.2 | V | |||
Reference output current(2) | 100 | nA | ||||
REFERENCE INPUT | ||||||
VEXTIO | Input voltage range | External Reference Mode | 0.6 | 1.2 | 1.25 | V |
Input resistance | 1 | MΩ | ||||
Small signal bandwidth | 472 | kHz | ||||
Input capacitance | 100 | pF | ||||
TEMPERATURE COEFFICIENTS | ||||||
Offset drift | ±1 | ppm/°C | ||||
Gain drift | with external reference | ±15 | ppm/°C | |||
with internal reference | ±30 | ppm/°C | ||||
Reference voltage drift | ±8 | ppm/°C | ||||
POWER SUPPLY(3) | ||||||
AVDD, IOVDD, PLLAVDD | 3.14 | 3.3 | 3.46 | V | ||
CLKVDD, DACVDD, DIGVDD | 1.14 | 1.2 | 1.26 | V | ||
IOVDD2 | 1.71 | 3.3 | 3.45 | V | ||
PSRR | Power supply rejection ratio | DC tested | ±0.25 | %FSR/V | ||
POWER CONSUMPTION | ||||||
I(AVDD) | Analog supply current(4) | MODE 1(5)
fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, 20mA FS output, IF = 200MHz |
135 | 165 | mA | |
I(DIGVDD) | Digital supply current | 740 | 820 | mA | ||
I(DACVDD) | DAC supply current | 40 | 60 | mA | ||
I(CLKVDD) | Clock supply current | 100 | 120 | mA | ||
P | Power dissipation | 1500 | 1750 | mW | ||
I(AVDD) | Analog supply current(4) | MODE 2 fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL disabled, 20mA FS output, IF = 200MHz |
125 | mA | ||
I(DIGVDD) | Digital supply current | 740 | mA | |||
I(DACVDD) | DAC supply current | 45 | mA | |||
I(CLKVDD) | Clock supply current | 75 | mA | |||
P | Power dissipation | 1440 | mW | |||
I(AVDD) | Analog supply current(4) | MODE 3 fDAC = 625MSPS, 2x interpolation, Mixer on, QMC on, invsinc off, PLL disabled, 20mA FS output, IF = 200MHz |
120 | mA | ||
I(DIGVDD) | Digital supply current | 370 | mA | |||
I(DACVDD) | DAC supply current | 25 | mA | |||
I(CLKVDD) | Clock supply current | 45 | mA | |||
P | Power dissipation | 925 | mW | |||
I(AVDD) | Analog supply current(4) | MODE 4 fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, Channels A/B/C/D output sleep, IF = 200MHz, |
50 | mA | ||
I(DIGVDD) | Digital supply current | 750 | mA | |||
I(DACVDD) | DAC supply current | 40 | mA | |||
I(CLKVDD) | Clock supply current | 100 | mA | |||
P | Power dissipation | 1240 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 5 Power-Down mode: No clock, DAC on sleep mode (clock receiver sleep), Channels A/B/C/D output sleep, static data pattern |
40 | mA | ||
I(DIGVDD) | Digital supply current | 10 | mA | |||
I(DACVDD) | DAC supply current | 5 | mA | |||
I(CLKVDD) | Clock supply current | 15 | mA | |||
P | Power dissipation | 150 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 6 fDAC = 1GSPS, 2x interpolation, Mixer off, QMC off, invsinc off, PLL enabled, 20mA FS output, IF = 200MHz |
140 | mA | ||
I(DIGVDD) | Digital supply current | 360 | mA | |||
I(DACVDD) | DAC supply current | 30 | mA | |||
I(CLKVDD) | Clock supply current | 90 | mA | |||
P | Power dissipation | 1040 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 7 fDAC = 1GSPS, 2x interpolation, Mixer off, QMC off, invsinc off, PLL disabled, 20mA FS output, IF = 200MHz |
120 | mA | ||
I(DIGVDD) | Digital supply current | 370 | mA | |||
I(DACVDD) | DAC supply current | 30 | mA | |||
I(CLKVDD) | Clock supply current | 65 | mA | |||
P | Power dissipation | 960 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1) | ||||||||
VA,B+ | Logic high differential input voltage threshold | 200 | mV | |||||
VA,B– | Logic low differential input voltage threshold | –200 | mV | |||||
VCOM | Input Common Mode | 1.0 | 1.2 | 1.6 | V | |||
ZT | Internal termination | 85 | 110 | 135 | Ω | |||
CL | LVDS Input capacitance | 2 | pF | |||||
fINTERL | Interleaved LVDS data transfer rate | 1250 | MSPS | |||||
fDATA | Input data rate | 625 | MSPS | |||||
CLOCK INPUT (DACCLKP/N) | ||||||||
Differential voltage(2) | 0.4 | 1.0 | V | |||||
OUTPUT STROBE (OSTRP/N) | ||||||||
Differential voltage | 0.4 | 1.0 | V | |||||
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA | ||||||||
VIH | High-level input voltage | 0.7 x IOVDD2 | V | |||||
VIL | Low-level input voltage | 0.3 x IOVDD2 | V | |||||
IIH | High-level input current | -40 | 40 | µA | ||||
IIL | Low-level input current | -40 | 40 | µA | ||||
CI | CMOS Input capacitance | 2 | pF | |||||
VOH | ALARM, SDO, SDIO | Iload = –100 μA | IOVDD2 – 0.2 | V | ||||
Iload = –2 mA | 0.8 x IOVDD2 | V | ||||||
VOL | ALARM, SDO, SDIO | Iload = 100 μA | 0.2 | V | ||||
Iload = 2 mA | 0.5 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG OUTPUT(1) | ||||||
fDAC | Maximum DAC rate | PLL OFF | 1250 | MSPS | ||
PLL ON | 1000 | |||||
AC PERFORMANCE(2) | ||||||
SFDR | Spurious free dynamic range (0 to fDAC/2) Tone at 0 dBFS |
fDAC = 1.25 GSPS, fOUT = 20 MHz | 73 | dBc | ||
fDAC = 1.25 GSPS, fOUT = 50 MHz | 70 | |||||
fDAC = 1.25 GSPS, fOUT = 70 MHz | 66 | |||||
IMD3 | Third-order two-tone intermodulation distortion Each tone at –12 dBFS |
fDAC = 1.25 MSPS, fOUT = 30 ± 0.5 MHz | 87 | dBc | ||
fDAC = 1.25 GSPS, fOUT = 50 ± 0.5 MHz | 85 | |||||
fDAC = 1.25 GSPS, fOUT = 100 ± 0.5 MHz | 78 | |||||
NSD | Noise Spectral Density(3)
Tone at 0dBFS |
fDAC = 1.25 GSPS, fOUT = 10 MHz | 160 | dBc/Hz | ||
fDAC = 1.25 GSPS, fOUT = 80 MHz | 155 | |||||
ACLR(3) | Adjacent channel leakage ratio, single carrier | fDAC = 1.2288 GSPS, fOUT = 30.72 MHz | 77 | dBc | ||
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz | 74 | |||||
Alternate channel leakage ratio, single carrier | fDAC = 1.2288 GSPS, fOUT = 30.72 MHz | 82 | ||||
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz | 80 | |||||
Channel Isolation | fDAC = 1.25 GSPS, fOUT = 10 MHz | 95 | dBc |
MIN | NOM | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
CLOCK INPUT (DACCLKP/N) | ||||||||
Duty cycle | 40% | 60% | ||||||
DACCLKP/N input frequency | 1250 | MHz | ||||||
OUTPUT STROBE (OSTRP/N) | ||||||||
fOSTR | Frequency | fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer, fDACCLK is DACCLK frequency in MHz | fDACCLK / (8 x interp) |
MHz | ||||
Duty cycle | 50% | |||||||
DIGITAL INPUT TIMING SPECIFICATIONS | ||||||||
Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching | ||||||||
ts(DATA) | Setup time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N | ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N | Config36 Setting | |||||
datadly | clkdly | |||||||
0 | 0 | 150 | ps | |||||
0 | 1 | 100 | ||||||
0 | 2 | 50 | ||||||
0 | 3 | 0 | ||||||
0 | 4 | -50 | ||||||
0 | 5 | -100 | ||||||
0 | 6 | -150 | ||||||
0 | 7 | -200 | ||||||
1 | 0 | 200 | ||||||
2 | 0 | 250 | ||||||
3 | 0 | 300 | ||||||
4 | 0 | 350 | ||||||
5 | 0 | 400 | ||||||
6 | 0 | 450 | ||||||
7 | 0 | 500 | ||||||
th(DATA) | Hold time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid after either edge of DATACLKP/N | ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N | Config36 Setting | ps | ||||
datadly | clkdly | |||||||
0 | 0 | 400 | ||||||
0 | 1 | 450 | ||||||
0 | 2 | 500 | ||||||
0 | 3 | 550 | ||||||
0 | 4 | 600 | ||||||
0 | 5 | 650 | ||||||
0 | 6 | 700 | ||||||
0 | 7 | 750 | ||||||
1 | 0 | 350 | ||||||
2 | 0 | 300 | ||||||
3 | 0 | 250 | ||||||
4 | 0 | 200 | ||||||
5 | 0 | 150 | ||||||
6 | 0 | 100 | ||||||
7 | 0 | 50 | ||||||
t(ISTR_SYNC) | ISTRP/N and SYNCP/N pulse width | fDATACLK is DATACLK frequency in MHz | 1/2fDATACLK | ns | ||||
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(1) | ||||||||
ts(OSTR) | Setup time, OSTRP/N valid to rising edge of DACCLKP/N | –100 | ps | |||||
th(OSTR) | Hold time, OSTRP/N valid after rising edge of DACCLKP/N | 500 | ps | |||||
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING(2) | ||||||||
ts(SYNC_PLL) | Setup time, SYNCP/N valid to rising edge of DACCLKP/N | 200 | ps | |||||
th(SYNC_PLL) | Hold time, SYNCP/N valid after rising edge of DACCLKP/N | 300 | ps | |||||
TIMING SERIAL PORT | ||||||||
ts(SDENB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
ts(SDIO) | Setup time, SDIO valid to rising edge of SCLK | 10 | ns | |||||
th(SDIO) | Hold time, SDIO valid to rising edge of SCLK | 5 | ns | |||||
t(SCLK) | Period of SCLK | Register config6 read (temperature sensor read) | 1 | µs | ||||
All other registers | 100 | ns | ||||||
td(Data) | Data output delay after falling edge of SCLK | 10 | ns | |||||
tRESET | Minimum RESETB pulse width | 25 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG OUTPUT(1) | |||||||
ts(DAC) | Output settling time to 0.1% | Transition: Code 0x0000 to 0xFFFF | 10 | ns | |||
tpd | Output propagation delay | DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). | 2 | ns | |||
tr(IOUT) | Output rise time 10% to 90% | 220 | ps | ||||
tf(IOUT) | Output fall time 90% to 10% | 220 | ps | ||||
Digital latency | No interpolation, FIFO on, Mixer off, QMC off, Inverse sinc off | 128 | DAC clock cycles | ||||
2x Interpolation | 216 | ||||||
4x Interpolation | 376 | ||||||
8x Interpolation | 726 | ||||||
16x Interpolation | 1427 | ||||||
Fine mixer | 24 | ||||||
QMC | 16 | ||||||
Inverse sinc | 20 | ||||||
Power-up Time |
DAC wake-up time | IOUT current settling to 1% of IOUTFS from output sleep | 2 | µs | |||
DAC sleep time | IOUT current settling to less than 1% of IOUTFS in output sleep | 2 |