The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS.
The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement.
A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package.
The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC34SH84 | NFBGA (196) | 12.00 mm x 12.00 mm |
Changes from D Revision (October 2012) to E Revision
Changes from C Revision (October 2012) to D Revision
Changes from B Revision (July 2012) to C Revision
Changes from A Revision (June 2012) to B Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
AVDD | D10, E11, F11, G11, H11, J11, K11, L10 | I | Analog supply voltage. (3.3 V) | |
ALARM | N12 | O | CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active-high, but can be changed to active-low via the config0 alarm_out_pol control bit. | |
BIASJ | H12 | O | Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>. | |
CLKVDD | C12, K12 | I | Internal clock buffer supply voltage. (1.35 V). It is recommended to isolate this supply from DIGVDD and DACVDD. | |
DAB[15..0]P | A7, A6, A5, A4, A3, A2, A1, C4, C2, D4, D2, E4, E2, F4, F2, G4 | I | LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is double data rate (DDR). | |
DAB15P is the most-significant data bit (MSB). DAB0P is the least-significant data bit (LSB). |
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The order of the bus can be reversed via the config2 revbus bit. | ||||
DAB[15..0]N | B7, B6, B5, B4, B3, B2, B1, C3, C1, D3, D1, E3, E1, F3, F1, G3 | I | LVDS negative input data bits 0 through 15 for the AB-channel path. (See the preceding DAB[15:0]P description.) | |
DCD[15..0]P | H4, J4, J2, K4, K2, L4, L2, M4, M2, N1, N2, N3, N4, N5, N6, N7 | I | LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is double data rate (DDR). | |
DCD15P is the most-significant data bit (MSB). DCD0P is the least-significant data bit (LSB). |
||||
The order of the bus can be reversed via the config2 revbus bit. | ||||
DCD[15..0]N | H3, J3, J1, K3, K1, L3, L1, M3, M1, P1, P2, P3, P4, P5, P6, P7 | I | LVDS negative input data bits 0 through 15 for the CD-channel path. (See the preceding DCD[15:0]P description.) | |
DACCLKP | A12 | I | Positive external LVPECL clock input for DAC core with a self-bias | |
DACCLKN | A11 | I | Complementary external LVPECL clock input for DAC core. (See the DACCLKP description.) | |
DACVDD | D9, E9, E10, F10, G10, H10, J10, K10, K9, L9 | I | DAC core supply voltage. (1.35 V). It is recommended to isolate this supply from CLKVDD and DIGVDD. | |
DATACLKP | G2 | I | LVDS positive input data clock. Internal 100-Ω termination resistor. Input data DAB[15:0]P/N and DCD[15:0]P/N are latched on both edges of DATACLKP/N (double data rate). | |
DATACLKN | G1 | I | LVDS negative input data clock. (See the DATACLKP description.) | |
DIGVDD | E5, E6, E7, F5, J5, K5, K6, K7 | I | Digital supply voltage. (1.3 V). It is recommended to isolate this supply from CLKVDD and DACVDD. | |
EXTIO | G12 | I/O | Used as an external reference input when the internal reference is disabled through config27 extref_ena = 1. Used as an internal reference output when config27 extref_ena = 0 (default). Requires a 0.1-μF decoupling capacitor to AGND when used as a reference output. | |
ISTRP/ PARITYABP |
H2 | I | LVDS input strobe positive input. Internal 100-Ω termination resistor The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital blocks, and/or to act as a parity input for the AB-data bus. These functions are captured with the rising edge of DATACLKP/N. This signal should be edge-aligned with DAB[15:0]P/N and DCD[15:0]P/N. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. |
|
ISTRN/ PARITYABN |
H1 | I | LVDS input strope negative input. (See the ISTRP/PARITYABP description.) | |
GND | A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, G9, G13, G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 | I | These pins are ground for all supplies. | |
IOUTAP | B14 | O | A-channel DAC current output. Connect directly to ground if unused. | |
IOUTAN | C14 | O | A-channel DAC complementary current output. Connect directly to ground if unused. | |
IOUTBP | F14 | O | B-channel DAC current output. Connect directly to ground if unused. | |
IOUTBN | E14 | O | B-channel DAC complementary current output. Connect directly to ground if unused. | |
IOUTCP | J14 | O | C-channel DAC current output. Connect directly to ground if unused. | |
IOUTCN | K14 | O | C-channel DAC complementary current output. Connect directly to ground if unused. | |
IOUTDP | N14 | O | D-channel DAC current output. Connect directly to ground if unused. | |
IOUTDN | M14 | O | D-channel DAC complementary current output. Connect directly to ground if unused. | |
IOVDD | D5, D6, G5, H5, L5. L6 | I | Supply voltage for all LVDS I/O. (3.3 V) | |
IOVDD2 | L12 | I | Supply voltage for all CMOS I/O. (1.8 V to 3.3 V) This supply can range from 1.8 V to 3.3 V to change the input and output levels of the CMOS I/O. | |
LPF | D12 | I/O | PLL loop filter connection. If not using the clock-multiplying PLL, the LPF pin can be left unconnected. | |
OSTRP | A9 | I | Optional LVPECL output strobe positive input. This positive-negative pair is captured with the rising edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in dual-sync-sources mode. If unused it can be left unconnected. | |
OSTRN | B9 | I | Optional LVPECL output strobe negative input. (See the OSTRP description.) | |
PARITYCDP | N8 | I | Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an internal 100-Ω termination resistor. If unused, it can be left unconnected. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. |
|
PARITYCDN | P8 | I | Optional LVDS negative input parity bit for the CD-data bus. | |
PLLAVDD | C11, D11 | I | PLL analog supply voltage (3.3 V) | |
SCLK | P9 | I | Serial interface clock. Internal pulldown | |
SDENB | P10 | I | Active-low serial data enable, always an input to the DAC34SH84. Internal pullup | |
SDIO | P11 | I/O | Serial interface data. Bidirectional in 3-pin mode (default) and unidirectional 4-pin mode. Internal pulldown | |
SDO | P12 | O | Unidirectional serial interface data in 4-pin mode. The SDO pin is in the high-impedance state in 3-pin interface mode (default). | |
SLEEP | N11 | I | Active-high asynchronous hardware power-down input. Internal pulldown | |
SYNCP | A8 | I | LVDS SYNC positive input. Internal 100-Ω termination resistor. If unused it can be left unconnected. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. | |
SYNCN | B8 | I | LVDS SYNC negative input | |
RESETB | N10 | I | Active-low input for chip RESET. Internal pullup | |
TXENA | N9 | I | Transmit enable active-high input. Internal pulldown To enable analog output data transmission, set sif_txenable in register config3 to 1 or pull the CMOS TXENA pin to high. To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin to low. The DAC output is forced to midscale. |
|
TESTMODE | L11 | I | This pin is used for factory testing. Internal pulldown. Leave unconnected for normal operation | |
VFUSE | D7, L7 | I | Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to DACVDD or DIGVDD for normal operation |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range(2) | DACVDD, DIGVDD, CLKVDD | –0.5 | 1.5 | V |
VFUSE | –0.5 | 1.5 | V | |
IOVDD, IOVDD2 | –0.5 | 4 | V | |
AVDD, PLLAVDD | –0.5 | 4 | V | |
Pin voltage range(2) | DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N, SYNCP/N | –0.5 | IOVDD + 0.5 | V |
DACCLKP/N, OSTRP/N | –0.5 | CLKVDD + 0.5 | V | |
ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, TXENA | –0.5 | IOVDD2 + 0.5 | V | |
IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N | –1.0 | AVDD + 0.5 | V | |
EXTIO, BIASJ | –0.5 | AVDD + 0.5 | V | |
LPF | –0.5 | PLLAVDD + 0.5 | V | |
Peak input current (any input) | 20 | mA | ||
Peak total input current (all inputs) | –30 | mA | ||
Absolute maximum junction temperature, TJ | 150 | °C | ||
Storage temperature range, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
TJ | Recommended operating junction temperature | 105 | °C | ||
Maximum rated operating junction temperature(1) | 125 | ||||
TA | Recommended free-air temperature | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | DAC34SH84 | UNIT | |
---|---|---|---|
ZAY (NFBGA) | |||
196 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 37.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 6.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 16.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | NA | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Resolution | 16 | Bits | ||||
DC ACCURACY | ||||||
DNL | Differential nonlinearity | 1 LSB = IOUTFS / 216 | ±2 | LSB | ||
INL | Integral nonlinearity | ±4 | LSB | |||
ANALOG OUTPUT | ||||||
Coarse gain linearity | ±0.04 | LSB | ||||
Offset error | Mid-code offset | ±0.001 | %FSR | |||
Gain error | With external reference | ±2 | %FSR | |||
With internal reference | ±2 | %FSR | ||||
Gain mismatch | With internal reference | ±2 | %FSR | |||
Full-scale output current | 10 | 20 | 30 | mA | ||
Output compliance range | –0.5 | 0.6 | V | |||
Output resistance | 300 | kΩ | ||||
Output capacitance | 5 | pF | ||||
REFERENCE OUTPUT | ||||||
VREF | Reference output voltage | 1.2 | V | |||
Reference output current(2) | 100 | nA | ||||
REFERENCE INPUT | ||||||
VEXTIO | Input voltage range | External reference mode | 0.6 | 1.2 | 1.25 | V |
Input resistance | 1 | MΩ | ||||
Small-signal bandwidth | 472 | kHz | ||||
Input capacitance | 100 | pF | ||||
TEMPERATURE COEFFICIENTS | ||||||
Offset drift | ±1 | ppm / °C | ||||
Gain drift | With external reference | ±15 | ppm / °C | |||
With internal reference | ±30 | ppm / °C | ||||
Reference voltage drift | ±8 | ppm / °C | ||||
POWER SUPPLY(3) | ||||||
AVDD, IOVDD, PLLAVDD | 3.14 | 3.3 | 3.46 | V | ||
DIGVDD | 1.25 | 1.3 | 1.35 | V | ||
CLKVDD, DACVDD | 1.3 | 1.35 | 1.4 | V | ||
IOVDD2 | 1.71 | 3.3 | 3.45 | V | ||
PSRR | Power-supply rejection ratio | DC tested | ±0.25 | %FSR / V | ||
POWER CONSUMPTION | ||||||
I(AVDD) | Analog supply current(4) | Mode 1 fDAC = 1.5 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL enabled, 20-mA FS output, IF = 200 MHz |
135 | 165 | mA | |
I(DIGVDD) | Digital supply current | 885 | 950 | mA | ||
I(DACVDD) | DAC supply current | 45 | 60 | mA | ||
I(CLKVDD) | Clock supply current | 127 | 145 | mA | ||
P | Power dissipation | 1828 | 2056 | mW | ||
I(AVDD) | Analog supply current(4) | Mode 2 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL disabled, 20-mA FS output, IF = 7.3 MHz |
115 | mA | ||
I(DIGVDD) | Digital supply current | 770 | mA | |||
I(DACVDD) | DAC supply current | 40 | mA | |||
I(CLKVDD) | Clock supply current | 95 | mA | |||
P | Power dissipation | 1562 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 3 fDAC = 737.28 MSPS, 2x interpolation, mixer on, QMC on, invsinc off, PLL disabled, 20-mA FS output, IF = 7.3 MHz |
115 | mA | ||
I(DIGVDD) | Digital supply current | 470 | mA | |||
I(DACVDD) | DAC supply current | 21 | mA | |||
I(CLKVDD) | Clock supply current | 55 | mA | |||
P | Power dissipation | 1093 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 4 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL enabled, IF = 7.3 MHz, channels A/B/C/D output sleep |
40 | mA | ||
I(DIGVDD) | Digital supply current | 710 | mA | |||
I(DACVDD) | DAC supply current | 50 | mA | |||
I(CLKVDD) | Clock supply current | 90 | mA | |||
P | Power dissipation | 1160 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 5 Power-down mode: no clock, DAC on sleep mode (clock receiver sleep), channels A/B/C/D output sleep, static data pattern |
28 | mA | ||
I(DIGVDD) | Digital supply current | 17 | mA | |||
I(DACVDD) | DAC supply current | 0 | mA | |||
I(CLKVDD) | Clock supply current | 20 | mA | |||
P | Power dissipation | 142 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 6 fDAC = 1 GSPS, 2x interpolation, mixer off, QMC off, invsinc off, PLL enabled, 20-mA FS output, IF = 7.3 MHz |
130 | mA | ||
I(DIGVDD) | Digital supply current | 570 | mA | |||
I(DACVDD) | DAC supply current | 25 | mA | |||
I(CLKVDD) | Clock supply current | 98 | mA | |||
P | Power dissipation | 1336 | mA | |||
I(AVDD) | Analog supply current(4) | Mode 7 fDAC = 1 GSPS, 2x interpolation, mixer off,QMC off, invsinc off, PLL disabled, 20-mA FS output, IF = 7.3 MHz |
115 | mA | ||
I(DIGVDD) | Digital supply current | 335 | mA | |||
I(DACVDD) | DAC supply current | 23 | mA | |||
I(CLKVDD) | Clock supply current | 70 | mA | |||
P | Power dissipation | 940 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 8 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL disabled, IF = 7.3 MHz, channels A/B/C/D output sleep |
45 | mA | ||
I(DIGVDD) | Digital supply current | 655 | mA | |||
I(DACVDD) | DAC supply current | 30 | mA | |||
I(CLKVDD) | Clock supply current | 95 | mA | |||
P | Power dissipation | 1169 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1) | ||||||||
VA,B+ | Logic-high differential input voltage threshold | 200 | mV | |||||
VA,B– | Logic-low differential input voltage threshold | –200 | mV | |||||
VCOM | Input common mode | 1 | 1.2 | 1.6 | V | |||
ZT | Internal termination | 85 | 110 | 135 | Ω | |||
CL | LVDS input capacitance | 2 | pF | |||||
fINTERL | Interleaved LVDS data transfer rate | 1500 | MSPS | |||||
fDATA | Input data rate | 750 | MSPS | |||||
CLOCK INPUT (DACCLKP/N) | ||||||||
Differential voltage(2) | |DACCLKP - DACCLKN| | 0.4 | 1 | V | ||||
Internally biased common-mode voltage | 0.2 | V | ||||||
Single-ended swing level | –0.4 | V | ||||||
OUTPUT STROBE (OSTRP/N) | ||||||||
Differential voltage | |OSTRP-OSTRN| | 0.4 | 1.0 | V | ||||
Internally biased common-mode voltage | 0.2 | V | ||||||
Single-ended swing level | –0.4 | V | ||||||
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA | ||||||||
VIH | High-level input voltage | 0.7 × IOVDD2 | V | |||||
VIL | Low-level input voltage | 0.3 × IOVDD2 | V | |||||
IIH | High-level input current | –40 | 40 | µA | ||||
IIL | Low-level input current | –40 | 40 | µA | ||||
CI | CMOS input capacitance | 2 | pF | |||||
VOH | ALARM, SDO, SDIO | Iload = –100 μA | IOVDD2 – 0.2 | V | ||||
Iload = –2 mA | 0.8 × IOVDD2 | V | ||||||
VOL | ALARM, SDO, SDIO | Iload = 100 μA | 0.2 | V | ||||
Iload = 2 mA | 0.5 | V | ||||||
PHASE-LOCKED LOOP | ||||||||
PLL/VCO operating frequency | PLL_vco = 011110 (30) | 2940 | 2957 | MHz | ||||
PLL_vco = 100010 (34) | 2957 | 3000 | ||||||
PLL_vco = 100110 (38) | 3000 | 3043 | ||||||
PLL_vco = 101010 (42) | 3034 | 3086 | ||||||
PLL_vco = 101110 (46) | 3069 | 3120 | ||||||
PLL_vco = 110010 (50) | 3103 | 3163 | ||||||
PLL_vco = 110110 (54) | 3128 | 3215 | ||||||
PLL_vco = 111010 (58) | 3170 | 3257 | ||||||
PLL_vco = 111111 (63) | 3215 | 3300 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
AC PERFORMANCE(1) | ||||||
SFDR | Spurious-free dynamic range, (0 to fDAC / 2) tone at 0 dBFS |
fDAC = 1.5 GSPS, fOUT = 20 MHz | 78 | dBc | ||
fDAC = 1.5 GSPS, fOUT = 50 MHz | 74 | |||||
fDAC = 1.5 GSPS, fOUT = 70 MHz | 71 | |||||
IMD3 | Third-order two-tone intermodulation distortion, each tone at –12 dBFS |
fDAC = 1.5 GSPS, fOUT = 30 ± 0.5 MHz | 87 | dBc | ||
fDAC = 1.5 GSPS, fOUT = 50 ± 0.5 MHz | 85 | |||||
fDAC = 1.5 GSPS, fOUT = 100 ± 0.5 MHz | 78 | |||||
NSD | Noise spectral density,(2)
tone at 0 dBFS |
fDAC = 1.5 GSPS, fOUT = 10 MHz | 160 | dBc / Hz | ||
fDAC = 1.5 GSPS, fOUT = 80 MHz | 158 | |||||
ACLR(2) | Adjacent-channel leakage ratio, single carrier | fDAC = 1.47456 GSPS, fOUT = 30 MHz | 76 | dBc | ||
fDAC = 1.47456 GSPS, fOUT = 153 MHz | 75 | |||||
Alternate-channel leakage ratio, single carrier | fDAC = 1.47456 GSPS, fOUT = 30 MHz | 86 | ||||
fDAC = 1.47456 GSPS, fOUT = 153 MHz | 82 | |||||
Channel isolation | fDAC = 1.5 GSPS, fOUT = 40 MHz | 101 | dBc |
MIN | NOM | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
CLOCK INPUT (DACCLKP/N) | ||||||||
Duty cycle | 40% | 60% | ||||||
DACCLKP/N input frequency | 1500 | MHz | ||||||
OUTPUT STROBE (OSTRP/N) | ||||||||
fOSTR | Frequency | fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer, fDACCLK is DACCLK frequency in MHz | fDACCLK / (8 x interp) |
MHz | ||||
Duty cycle | 50% | |||||||
DIGITAL INPUT TIMING SPECIFICATIONS | ||||||||
Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching | ||||||||
ts(DATA) | Setup time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N | ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N | Config36 Setting | |||||
datadly | clkdly | |||||||
0 | 0 | 30 | ps | |||||
0 | 1 | –10 | ||||||
0 | 2 | –50 | ||||||
0 | 3 | –90 | ||||||
0 | 4 | –130 | ||||||
0 | 5 | –170 | ||||||
0 | 6 | –210 | ||||||
0 | 7 | –250 | ||||||
1 | 0 | 50 | ||||||
2 | 0 | 90 | ||||||
3 | 0 | 130 | ||||||
4 | 0 | 170 | ||||||
5 | 0 | 210 | ||||||
6 | 0 | 250 | ||||||
7 | 0 | 290 | ||||||
th(DATA) | Hold time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid after either edge of DATACLKP/N | ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N | Config36 Setting | ps | ||||
datadly | clkdly | |||||||
0 | 0 | 200 | ||||||
0 | 1 | 240 | ||||||
0 | 2 | 280 | ||||||
0 | 3 | 320 | ||||||
0 | 4 | 360 | ||||||
0 | 5 | 400 | ||||||
0 | 6 | 440 | ||||||
0 | 7 | 480 | ||||||
1 | 0 | 190 | ||||||
2 | 0 | 150 | ||||||
3 | 0 | 110 | ||||||
4 | 0 | 70 | ||||||
5 | 0 | 30 | ||||||
6 | 0 | –10 | ||||||
7 | 0 | –50 | ||||||
t(ISTR_SYNC) | ISTRP/N and SYNCP/N pulse width | fDATACLK is DATACLK frequency in MHz | 1/2fDATACLK | ns | ||||
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(1) | ||||||||
ts(OSTR) | Setup time, OSTRP/N valid to rising edge of DACCLKP/N | –80 | ps | |||||
th(OSTR) | Hold time, OSTRP/N valid after rising edge of DACCLKP/N | 220 | ps | |||||
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING(2) | ||||||||
ts(SYNC_PLL) | Setup time, SYNCP/N valid to rising edge of DACCLKP/N | 150 | ps | |||||
th(SYNC_PLL) | Hold time, SYNCP/N valid after rising edge of DACCLKP/N | 250 | ps | |||||
TIMING SERIAL PORT | ||||||||
ts(SDENB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
ts(SDIO) | Setup time, SDIO valid to rising edge of SCLK | 10 | ns | |||||
th(SDIO) | Hold time, SDIO valid to rising edge of SCLK | 5 | ns | |||||
t(SCLK) | Period of SCLK | Register config6 read (temperature sensor read) | 1 | µs | ||||
All other registers | 100 | ns | ||||||
td(Data) | Data output delay after falling edge of SCLK | 10 | ns | |||||
tRESET | Minimum RESETB pulse width | 25 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG OUTPUT(1) | |||||||
ts(DAC) | Output settling time to 0.1% | Transition: Code 0x0000 to 0xFFFF | 10 | ns | |||
tpd | Output propagation delay | DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). | 2 | ns | |||
tr(IOUT) | Output rise time 10% to 90% | 220 | ps | ||||
tf(IOUT) | Output fall time 90% to 10% | 220 | ps | ||||
Digital latency | No interpolation, FIFO on, Mixer off, QMC off, Inverse sinc off | 128 | DAC clock cycles | ||||
2x Interpolation | 216 | ||||||
4x Interpolation | 376 | ||||||
8x Interpolation | 726 | ||||||
16x Interpolation | 1427 | ||||||
Fine mixer | 24 | ||||||
QMC | 16 | ||||||
Inverse sinc | 20 | ||||||
Power-up Time |
DAC wake-up time | IOUT current settling to 1% of IOUTFS from output sleep | 2 | µs | |||
DAC sleep time | IOUT current settling to less than 1% of IOUTFS in output sleep | 2 |