The DAC756x, DAC816x, and DAC856x devices are low-power, voltage-output, dual-channel, 16-, 14-, and 12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V,
4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin.
These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile three-wire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACxx62 devices incorporate a power-on-reset circuit that ensures the DAC output powers up and remains at zero scale until a valid code is written to the device, whereas the DACxx63 devices similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 550 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment.
The DACxx62 devices are drop-in and function-compatible with each other, as are the DACxx63 devices. The entire family is available in MSOP-10 and SON-10 packages.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC8562 | VSSOP (10), WSON (10) |
3.00 mm × 3.00 mm |
DAC8162 | ||
DAC7562 |
Changes from D Revision (August 2012) to E Revision
Changes from C Revision (June 2011, first official release) to D Revision
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE(1) | ||||||
DAC856x | Resolution | 16 | Bits | |||
Relative accuracy | Using line passing through codes 512 and 65,024 | ±4 | ±12 | LSB | ||
Differential nonlinearity | 16-bit monotonic | ±0.2 | ±1 | LSB | ||
DAC816x | Resolution | 14 | Bits | |||
Relative accuracy | Using line passing through codes 128 and 16,256 | ±1 | ±3 | LSB | ||
Differential nonlinearity | 14-bit monotonic | ±0.1 | ±0.5 | LSB | ||
DAC756x | Resolution | 12 | Bits | |||
Relative accuracy | Using line passing through codes 32 and 4,064 | ±0.3 | ±0.75 | LSB | ||
Differential nonlinearity | 12-bit monotonic | ±0.05 | ±0.25 | LSB | ||
Offset error | Extrapolated from two-point line(1), unloaded | ±1 | ±4 | mV | ||
Offset error drift | ±2 | µV/°C | ||||
Full-scale error | DAC register loaded with all 1s | ±0.03 | ±0.2 | % FSR | ||
Zero-code error | DAC register loaded with all 0s | 1 | 4 | mV | ||
Zero-code error drift | ±2 | µV/°C | ||||
Gain error | Extrapolated from two-point line(1), unloaded | ±0.01 | ±0.15 | % FSR | ||
Gain temperature coefficient | ±1 | ppm FSR/°C | ||||
OUTPUT CHARACTERISTICS(2) | ||||||
Output voltage range | 0 | AVDD | V | |||
Output voltage settling time(3) | DACs unloaded | 7 | µs | |||
RL = 1 MΩ | 10 | |||||
Slew rate | Measured between 20%–80% of a full-scale transition | 0.75 | V/µs | |||
Capacitive load stability | RL = ∞ | 1 | nF | |||
RL = 2 kΩ | 3 | |||||
Code-change glitch impulse | 1-LSB change around major carry | 0.1 | nV-s | |||
Digital feedthrough | SCLK toggling, SYNC high | 0.1 | nV-s | |||
Power-on glitch impulse | RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V | 40 | mV | |||
Channel-to-channel dc crosstalk | Full-scale swing on adjacent channel, External reference |
5 | µV | |||
Full-scale swing on adjacent channel, Internal reference |
15 | |||||
DC output impedance | At mid-scale input | 5 | Ω | |||
Short-circuit current | DAC outputs at full-scale, DAC outputs shorted to GND | 40 | mA | |||
Power-up time, including settling time | Coming out of power-down mode | 50 | µs | |||
AC PERFORMANCE(2) | ||||||
DAC output noise density | TA = 25°C, at mid-scale input, fOUT = 1 kHz | 90 | nV/√Hz | |||
DAC output noise | TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz | 2.6 | µVPP | |||
LOGIC INPUTS(2) | ||||||
Input-pin leakage current | –1 | ±0.1 | 1 | µA | ||
Logic input LOW voltage VIL | 0 | 0.8 | V | |||
Logic input HIGH voltage VIH | 0.7 × AVDD | AVDD | V | |||
Pin capacitance | 3 | pF | ||||
REFERENCE | ||||||
External reference current | External VREF = 2.5 V (when internal reference is disabled), all channels active using gain = 1 | 15 | µA | |||
Reference input impedance | Internal reference disabled, gain = 1 | 170 | kΩ | |||
Internal reference disabled, gain = 2 | 85 | |||||
REFERENCE OUTPUT | ||||||
Output voltage | TA = 25°C | 2.495 | 2.5 | 2.505 | V | |
Initial accuracy | TA = 25°C | –5 | ±0.1 | 5 | mV | |
Output-voltage temperature drift | 4 | 10 | ppm/°C | |||
Output-voltage noise | f = 0.1 Hz to 10 Hz | 12 | µVPP | |||
Output-voltage noise density (high-frequency noise) | TA = 25°C, f = 1 kHz, CL = 0 µF | 250 | nV/√Hz | |||
TA = 25°C, f = 1 MHz, CL = 0 µF | 30 | |||||
TA = 25°C, f = 1 MHz, CL = 4.7 µF | 10 | |||||
Load regulation, sourcing(4) | TA = 25°C | 20 | µV/mA | |||
Load regulation, sinking(4) | TA = 25°C | 185 | µV/mA | |||
Output-current load capability(2) | ±20 | mA | ||||
Line regulation | TA = 25°C | 50 | µV/V | |||
Long-term stability or drift (aging)(4) | TA = 25°C, time = 0 to 1900 hours | 100 | ppm | |||
Thermal hysteresis(4) | First cycle | 200 | ppm | |||
Additional cycles | 50 | |||||
POWER REQUIREMENTS(5) | ||||||
Power supply current (IDD) | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off | 0.25 | 0.5 | mA | ||
AVDD = 3.6 V to 5.5 V, normal mode, internal reference on | 0.9 | 1.6 | ||||
AVDD = 3.6 V to 5.5 V, power-down modes(6) | 0.55 | 2 | µA | |||
AVDD = 3.6 V to 5.5 V, power-down modes | 0.55 | 4 | ||||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference off | 0.2 | 0.4 | mA | |||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference on | 0.73 | 1.4 | ||||
AVDD = 2.7 V to 3.6 V, power-down modes(6) | 0.35 | 2 | µA | |||
AVDD = 2.7 V to 3.6 V, power-down modes | 0.35 | 3 | ||||
Power dissipation | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off | 0.9 | 2.75 | mW | ||
AVDD = 3.6 V to 5.5 V, normal mode, internal reference on | 3.2 | 8.8 | ||||
AVDD = 3.6 V to 5.5 V, power-down modes(6) | 2 | 11 | µW | |||
AVDD = 3.6 V to 5.5 V, power-down modes | 2 | 22 | ||||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference off | 0.54 | 1.44 | mW | |||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference on | 1.97 | 5 | ||||
AVDD = 2.7 V to 3.6 V, power-down modes(6) | 0.95 | 7.2 | µW | |||
AVDD = 2.7 V to 3.6 V, power-down modes | 0.95 | 10.8 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
Internal Reference Voltage vs Temperature | 5.5 V | Figure 2 | |
Internal Reference Voltage Temperature Drift Histogram | Figure 3 | ||
Internal Reference Voltage vs Load Current | Figure 4 | ||
Internal Reference Voltage vs Time | Figure 5 | ||
Internal Reference Noise Density vs Frequency | Figure 6 | ||
Internal Reference Voltage vs Supply Voltage | 2.7 V–5.5 V | Figure 7 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS | |||
Full-Scale Error vs Temperature | 5.5 V | Figure 16 | |
Gain Error vs Temperature | Figure 17 | ||
Offset Error vs Temperature | Figure 18 | ||
Zero-Code Error vs Temperature | Figure 19 | ||
Full-Scale Error vs Temperature | 2.7 V | Figure 63 | |
Gain Error vs Temperature | Figure 64 | ||
Offset Error vs Temperature | Figure 65 | ||
Zero-Code Error vs Temperature | Figure 66 | ||
LOAD REGULATION | |||
DAC Output Voltage vs Load Current | 5.5 V | Figure 30 | |
2.7 V | Figure 74 | ||
DIFFERENTIAL NONLINEARITY ERROR | |||
Differential Linearity Error vs Digital Input Code | T = –40°C | 5.5 V | Figure 9 |
T = 25°C | Figure 11 | ||
T = 125°C | Figure 13 | ||
Differential Linearity Error vs Temperature | Figure 15 | ||
Differential Linearity Error vs Digital Input Code | T = –40°C | 2.7 V | Figure 56 |
T = 25°C | Figure 58 | ||
T = 125°C | Figure 60 | ||
Differential Linearity Error vs Temperature | Figure 62 | ||
INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY) | |||
Linearity Error vs Digital Input Code | T = –40°C | 5.5 V | Figure 8 |
T = 25°C | Figure 10 | ||
T = 125°C | Figure 12 | ||
Linearity Error vs Temperature | Figure 14 | ||
Linearity Error vs Digital Input Code | T = –40°C | 2.7 V | Figure 55 |
T = 25°C | Figure 57 | ||
T = 125°C | Figure 59 | ||
Linearity Error vs Temperature | Figure 61 | ||
POWER-DOWN CURRENT | |||
Power-Down Current vs Temperature | 5.5 V | Figure 28 | |
Power-Down Current vs Power-Supply Voltage | 2.7 V – 5.5 V | Figure 29 | |
Power-Down Current vs Temperature | 2.7 V | Figure 73 | |
POWER-SUPPLY CURRENT | |||
Power-Supply Current vs Temperature | External VREF | 5.5 V | Figure 20 |
Internal VREF | Figure 21 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 22 | |
Internal VREF | Figure 23 | ||
Power-Supply Current Histogram | External VREF | Figure 24 | |
Internal VREF | Figure 25 | ||
Power-Supply Current vs Power-Supply Voltage | External VREF | 2.7 V – 5.5 V | Figure 26 |
Internal VREF | Figure 27 | ||
Power-Supply Current vs Temperature | External VREF | 3.6 V | Figure 49 |
Internal VREF | Figure 50 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 51 | |
Internal VREF | Figure 52 | ||
Power-Supply Current Histogram | External VREF | Figure 53 | |
Internal VREF | Figure 54 | ||
Power-Supply Current vs Temperature | External VREF | 2.7 V | Figure 67 |
Internal VREF | Figure 68 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 69 | |
Internal VREF | Figure 70 | ||
Power-Supply Current Histogram | External VREF | Figure 71 | |
Internal VREF | Figure 72 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
CHANNEL-TO-CHANNEL CROSSTALK | |||
Channel-to-Channel Crosstalk | 5-V Rising Edge | 5.5 V | Figure 43 |
5-V Falling Edge | Figure 44 | ||
CLOCK FEEDTHROUGH | |||
Clock Feedthrough | 500 kHz, Midscale | 5.5 V | Figure 48 |
2.7 V | Figure 87 | ||
GLITCH IMPULSE | |||
Glitch Impulse, 1-LSB Step | Rising Edge, Code 7FFFh to 8000h | 5.5 V | Figure 37 |
Falling Edge, Code 8000h to 7FFFh | Figure 38 | ||
Glitch Impulse, 4-LSB Step | Rising Edge, Code 7FFCh to 8000h | Figure 39 | |
Falling Edge, Code 8000h to 7FFCh | Figure 40 | ||
Glitch Impulse, 16-LSB Step | Rising Edge, Code 7FF0h to 8000h | Figure 41 | |
Falling Edge, Code 8000h to 7FF0h | Figure 42 | ||
Glitch Impulse, 1-LSB Step | Rising Edge, Code 7FFFh to 8000h | 2.7 V | Figure 79 |
Falling Edge, Code 8000h to 7FFFh | Figure 80 | ||
Glitch Impulse, 4-LSB Step | Rising Edge, Code 7FFCh to 8000h | Figure 81 | |
Falling Edge, Code 8000h to 7FFCh | Figure 82 | ||
Glitch Impulse, 16-LSB Step | Rising Edge, Code 7FF0h to 8000h | Figure 83 | |
Falling Edge, Code 8000h to 7FF0h | Figure 84 | ||
NOISE | |||
DAC Output Noise Density vs Frequency | External VREF | 5.5 V | Figure 45 |
Internal VREF | Figure 46 | ||
DAC Output Noise 0.1 Hz to 10 Hz | External VREF | Figure 47 | |
POWER-ON GLITCH | |||
Power-On Glitch | Reset to Zero Scale | 5.5 V | Figure 35 |
Reset to Midscale | Figure 36 | ||
Reset to Zero Scale | 2.7 V | Figure 85 | |
Reset to Midscale | Figure 86 | ||
SETTLING TIME | |||
Full-Scale Settling Time | Rising Edge, Code 0h to FFFFh | 5.5 V | Figure 31 |
Falling Edge, Code FFFFh to 0h | Figure 32 | ||
Half-Scale Settling Time | Rising Edge, Code 4000h to C000h | Figure 33 | |
Falling Edge, Code C000h to 4000h | Figure 34 | ||
Full-Scale Settling Time | Rising Edge, Code 0h to FFFFh | 2.7 V | Figure 75 |
Falling Edge, Code FFFFh to 0h | Figure 76 | ||
Half-Scale Settling Time | Rising Edge, Code 4000h to C000h | Figure 77 | |
Falling Edge, Code C000h to 4000h | Figure 78 |
The DAC756x, DAC816x, and DAC856x devices are low-power, voltage-output, dual-channel, 16-, 14-, and
12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin.
The DAC756x, DAC816x, and DAC856x architecture consists of two string DACs, each followed by an output buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift performance. Figure 88 shows a principal block diagram of the DAC architecture.
The input coding to the DAC756x, DAC816x, and DAC856x devices is straight binary, so the ideal output voltage is given by Equation 1:
where:
n = resolution in bits; either 12 (DAC756x), 14 (DAC816x) or 16 (DAC856x)
DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2n – 1.
VREF = DAC reference voltage; either VREFOUT from the internal 2.5-V reference or VREFIN from an
aaa external reference.
Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default
aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register.
aaa See the Gain Function section for more information.
The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string architecture results in monotonicity. The RDIVIDER switch is controlled by the gain registers (see the Gain Function section). Because the output amplifier has a gain of 2, RDIVIDER is not shorted when the DAC-n gain is set to 1 (default if internal reference is disabled), and is shorted when the DAC-n gain is set to 2 (default if internal reference is enabled).
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output range of 0 V to AVDD. It is capable of driving a load of 2 kΩ in parallel with 3 nF to GND. The typical slew rate is 0.75 V/µs, with a typical full-scale settling time of 14 µs as shown in Figure 31, Figure 32, Figure 75 and Figure 76.
The DAC756x, DAC816x, and DAC856x devices include a 2.5-V internal reference that is disabled by default. The internal reference is externally available at the VREFIN/VREFOUT pin. The internal reference output voltage is 2.5 V and can sink and source up to 20 mA.
A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering.
The internal reference of the DAC756x, DAC816x, and DAC856x devices is a bipolar transistor-based precision band-gap voltage reference. Figure 90 shows the basic band-gap topology. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R1. This voltage is amplified and added to the base-emitter voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to approximately 100 mA.
The DAC7562, DAC8162, and DAC8562 devices contain a power-on-reset circuit that controls the output voltage during power up. All device registers are reset as shown in Table 4. At power up, all DAC registers are filled with zeros and the output voltages of all DAC channels are set to zero volts. Each DAC channel remains that way until a valid load command is written to it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before applying power to the device. The internal reference is disabled by default and remains that way until a valid reference-change command is executed.
The DAC7563, DAC8163, and DAC8563 devices contain a power-on reset circuit that controls the output voltage during power up. At power up, all DAC registers are reset to mid-scale code and the output voltages of all DAC channels are set to VREFIN / 2 volts. Each DAC channel remains that way until a valid load command is written to it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before applying power to the device. The internal reference is powered off or down by default and remains that way until a valid reference-change command is executed. If using an external reference, it is acceptable to power on the VREFIN pin either at the same time as or after applying AVDD.
REGISTER | DEFAULT SETTING | |
---|---|---|
DAC and input registers | DACxx62 | Zero-scale |
DACxx63 | Mid-scale | |
LDAC registers | LDAC pin enabled for both channels | |
Power-down registers | DACs powered up | |
Internal reference register | Internal reference disabled | |
Gain registers | Gain = 1 for both channels |
When the device powers up, a POR circuit sets the device in default mode as shown in Table 4. The POR circuit requires specific AVDD levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, AVDD must be below 0.7 V for at least 1 ms. When AVDD drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on reset. When AVDD remains above 2.2 V, a power-on reset does not occur.
The DAC756x, DAC816x, and DAC856x devices have two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. The internal reference is forced to a powered-down state while both DAC channels are powered down, and is only enabled if any DAC channel is also in the normal mode of operation. For more information on the internal reference control, see the Internal Reference Enable Register section.
The DAC756x, DAC816x, and DAC856x DACs use four modes of operation. These modes are accessed by setting the serial interface command bits to 100. Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits DB5 and DB4 in the shift register. Table 5 and Table 6 show the different power-down options. For more information on how to set the DAC operating mode see Table 17.
DB5 | DB4 | DAC Modes of Operation |
---|---|---|
0 | 0 | Selected DACs power up (normal mode, default) |
0 | 1 | Selected DACs power down, output 1 kΩ to GND |
1 | 0 | Selected DACs power down, output 100 kΩ to GND |
1 | 1 | Selected DACs power down, output Hi-Z to GND |
DAC-B (DB1), DAC-A (DB0) | Operating Mode |
---|---|
0 | DAC-n does not change operating mode |
1 | DAC-n operating mode set to value on PD1 and PD0 |
It is possible to write to the DAC register or buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value.
The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. VOUT can be connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC power-down circuitry is shown in Figure 92.
The gain register controls the GAIN setting in the DAC transfer function:
The DAC756x, DAC816x, and DAC856x devices have a gain register for each channel. The gain for each channel, in Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference, and is automatically set to 1 when the internal reference is disabled (default). However, each channel can have either gain by setting the registers appropriately. The gain registers are accessible by setting the serial interface command bits to 000, address bits to 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 7 and Table 17 for the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2 when the internal reference is powered off or on, respectively. After the reference is powered off or on, the gain register is again accessible to change the gain.
DB1, DB0 | Value | Gain |
---|---|---|
DB0 | 0 | DAC-A uses gain = 2 (default with internal reference) |
1 | DAC-A uses gain = 1 (default with external reference) | |
DB1 | 0 | DAC-B uses gain = 2 (default with internal reference) |
1 | DAC-B uses gain = 1 (default with external reference) |
The DAC756x, DAC816x, and DAC856x devices contain a software reset feature. The software reset function is accessed by setting the serial interface command bits to 101. The software reset command contains two reset modes which are software-programmable by setting bit DB0 in the shift register. Table 8 and Table 17 show the available software reset commands.
DB0 | Registers Reset to Default Values |
---|---|
0 | DAC registers Input registers |
1 | DAC registers Input registers LDAC registers Power-down registers Internal reference register Gain registers |
The internal reference in the DAC756x, DAC816x, and DAC856x devices is disabled by default for debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up and powered down by setting the serial interface command bits to 111 and configuring DB0 (see Table 9). The internal reference is forced to a powered down state while both DAC channels are powered down, and can only be enabled if any DAC channel is in normal mode of operation. During the time that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the internal reference is disconnected from the VREFIN/VREFOUT pin (Hi-Z output).
DB0 | Internal Reference Configuration |
---|---|
0 | Disable internal reference and reset DACs to gain = 1 |
1 | Enable internal reference and reset DACs to gain = 2 |
To enable the internal reference, refer to the command structure in Table 17. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference is powered down until a valid write sequence powers up the internal reference. However, the internal reference is forced to a disabled state while both DAC channels are powered down, and remains disabled until either DAC channel is returned to the normal mode of operation. See DAC Power-Down Commands for more information on DAC channel modes of operation.
To disable the internal reference, refer to the command structure in Table 17. When performing a power cycle to reset the device, the internal reference is disabled (default mode).
The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 10. When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output voltages accordingly. The device exits clear mode on the 24th falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately according to Table 10.
DEVICE | DAC Output Entering Clear Mode |
---|---|
DAC8562, DAC8162, DAC7562 | Zero-scale |
DAC8563, DAC8163, DAC7563 | Mid-scale |
The DAC756x, DAC816x, and DAC856x devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs.
DAC756x, DAC816x, and DAC856x data updates can be performed either in synchronous or in asynchronous mode.
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered. LDAC must be returned high before the next serial command is initiated.
In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word (DB1 and DB0) using command bits C2, C1, and C0 (see Table 17). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel) and this DAC channel updates synchronously after the falling edge of the 24th SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin.
The combination of software and hardware simultaneous update functions is particularly useful in applications when updating a DAC channel, while keeping the other channel unaffected; see Table 11 and Table 17 for more information.
DB1, DB0 | Value | LDAC Pin Functionality |
---|---|---|
DB0 | 0 | DAC-A uses LDAC pin |
1 | DAC-A operates in synchronous mode | |
DB1 | 0 | DAC-B uses LDAC pin |
1 | DAC-B operates in synchronous mode |
The DAC756x, DAC816x, and DAC856x devices have a three-wire serial interface (SYNC, SCLK, and DIN; see the table) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.
The DAC756x, DAC816x, or DAC856x input shift register is 24 bits wide, consisting of two don’t care bits (DB23 to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). All 24 bits of data are loaded into the DAC under the control of the serial clock input, SCLK. DB23 (MSB) is the first bit that is loaded into the DAC shift register. DB23 is followed by the rest of the 24-bit word pattern, left-aligned. This configuration means that the first 24 bits of data are latched into the shift register, and any further clocking of data is ignored.
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the DAC756x, DAC816x, and DAC856x devices compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does not change the shift register data.
After receiving the 24th falling clock edge, the DAC756x, DAC816x, and DAC856x devices decode the three command bits, three address bits and 16 data bits to perform the required function, without waiting for a SYNC rising edge. After the 24th falling edge of SCLK is received, the SYNC line may be kept low or brought high. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1).
A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs. A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible.
In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 23rd falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 93).
When the DAC registers are being written to, the DAC756x, DAC816x, and DAC856x devices receive all 24 bits of data, ignore DB23 and DB22, and decode the next three bits (DB21 to DB19) in order to determine the DAC operating or control mode (see Table 12). Bits DB18 to DB16 are used to address the DAC channels (see Table 13).
C2 (DB21) |
C1 (DB20) |
C0 (DB19) |
Command |
---|---|---|---|
0 | 0 | 0 | Write to input register n (Table 13) |
0 | 0 | 1 | Software LDAC, update DAC register n (Table 13) |
0 | 1 | 0 | Write to input register n (Table 13) and update all DAC registers |
0 | 1 | 1 | Write to input register n and update DAC register n (Table 13) |
1 | 0 | 0 | Set DAC power up or -down mode |
1 | 0 | 1 | Software reset |
1 | 1 | 0 | Set LDAC registers |
1 | 1 | 1 | Enable or disable the internal reference |
A2 (DB18) |
A1 (DB17) |
A0 (DB16) |
Channel (n) |
---|---|---|---|
0 | 0 | 0 | DAC-A |
0 | 0 | 1 | DAC-B |
0 | 1 | 0 | Gain (only use with command 000) |
0 | 1 | 1 | Reserved |
1 | 0 | 0 | Reserved |
1 | 0 | 1 | Reserved |
1 | 1 | 0 | Reserved |
1 | 1 | 1 | DAC-A and DAC-B |
When writing to the DAC input registers the next 16, 14, or 12 bits of data that follow are decoded by the DAC to determine the equivalent analog output (see Table 14 through Table 16) . The data format is straight binary, with all 0s corresponding to 0-V output and all 1s corresponding to full-scale output. For all documentation purposes, the data format and representation used here is a true 16-bit pattern (that is, FFFFh data word for full scale) that the DAC756x, DAC816x, and DAC856x devices require.
COMMAND | ADDRESS | DATA | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
X(1) | X | C2 | C1 | C0 | A2 | A1 | A0 | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
DB23 | DB0 |
COMMAND | ADDRESS | DATA | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
X | X | C2 | C1 | C0 | A2 | A1 | A0 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | X | X | |
DB23 | DB0 |
COMMAND | ADDRESS | DATA | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
X | X | C2 | C1 | C0 | A2 | A1 | A0 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | X | X | X | X | |
DB23 | DB0 |
In additon to DAC input register updates, the DAC756x, DAC816x, and DAC856x devices support a number of functional mode commands (such as write to LDAC register, power down DACs and so on). The complete set of functional mode commands is shown in Table 17.
DB23-DB22 | Command | Address | Data | DESCRIPTION | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
C2 | C1 | C0 | A2 | A1 | A0 | DB15-DB6 | DB5 | DB4 | DB3-DB2 | DB1 | DB0 | ||
X(1) | 0 | 0 | 0 | 0 | 0 | 0 | 16-, 14-, or 12-bit DAC data | Write to DAC-A input register | |||||
0 | 0 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-B input register | |||||||||
1 | 1 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-A and DAC-B input registers | |||||||||
X | 0 | 1 | 0 | 0 | 0 | 0 | 16-, 14-, or 12-bit DAC data | Write to DAC-A input register and update all DACs | |||||
0 | 0 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-B input register and update all DACs | |||||||||
1 | 1 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-A and DAC-B input register and update all DACs | |||||||||
X | 0 | 1 | 1 | 0 | 0 | 0 | 16-, 14-, or 12-bit DAC data | Write to DAC-A input register and update DAC-A | |||||
0 | 0 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-B input register and update DAC-B | |||||||||
1 | 1 | 1 | 16-, 14-, or 12-bit DAC data | Write to DAC-A and DAC-B input register and update all DACs | |||||||||
X | 0 | 0 | 1 | 0 | 0 | 0 | X | Update DAC-A | |||||
0 | 0 | 1 | X | Update DAC-B | |||||||||
1 | 1 | 1 | X | Update all DACs | |||||||||
X | 0 | 0 | 0 | 0 | 1 | 0 | X | 0 | 0 | Gain: DAC-B gain = 2, DAC-A gain = 2 (default with internal VREF) | |||
0 | 1 | Gain: DAC-B gain = 2, DAC-A gain = 1 | |||||||||||
1 | 0 | Gain: DAC-B gain = 1, DAC-A gain = 2 | |||||||||||
1 | 1 | Gain: DAC-B gain = 1, DAC-A gain = 1 (power-on default) | |||||||||||
X | 1 | 0 | 0 | X | X | 0 | 0 | X | 0 | 1 | Power up DAC-A | ||
1 | 0 | Power up DAC-B | |||||||||||
1 | 1 | Power up DAC-A and DAC-B | |||||||||||
X | 1 | 0 | 0 | X | X | 0 | 1 | X | 0 | 1 | Power down DAC-A; 1 kΩ to GND | ||
1 | 0 | Power down DAC-B; 1 kΩ to GND | |||||||||||
1 | 1 | Power down DAC-A and DAC-B; 1 kΩ to GND | |||||||||||
X | 1 | 0 | 0 | X | X | 1 | 0 | X | 0 | 1 | Power down DAC-A; 100 kΩ to GND | ||
1 | 0 | Power down DAC-B; 100 kΩ to GND | |||||||||||
1 | 1 | Power down DAC-A and DAC-B; 100 kΩ to GND | |||||||||||
X | 1 | 0 | 0 | X | X | 1 | 1 | X | 0 | 1 | Power down DAC-A; Hi-Z | ||
1 | 0 | Power down DAC-B; Hi-Z | |||||||||||
1 | 1 | Power down DAC-A and DAC-B; Hi-Z | |||||||||||
X | 1 | 0 | 1 | X | X | X | 0 | Reset DAC-A and DAC-B input register and update all DACs | |||||
X | 1 | Reset all registers and update all DACs (Power-on-reset update) | |||||||||||
X | 1 | 1 | 0 | X | X | 0 | 0 | LDAC pin active for DAC-B and DAC-A | |||||
0 | 1 | LDAC pin active for DAC-B; inactive for DAC-A | |||||||||||
1 | 0 | LDAC pin inactive for DAC-B; active for DAC-A | |||||||||||
1 | 1 | LDAC pin inactive for DAC-B and DAC-A | |||||||||||
X | 1 | 1 | 1 | X | X | X | 0 | Disable internal reference and reset DACs to gain = 1 | |||||
X | 1 | Enable internal reference and reset DACs to gain = 2 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The internal reference of the DAC756x, DAC816x, and DAC856x devices does not require an external load capacitor for stability because it is stable without any capacitive load. However, for improved noise performance, an external load capacitor of 150 nF or larger connected to the VREFIN/VREFOUT output is recommended. Figure 94 shows the typical connections required for operation of the DAC756x, DAC816x, and DAC856x internal reference. A supply bypass capacitor at the AVDD input is also recommended.
The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV above the reference output voltage in an unloaded condition. For loaded conditions, see the Load Regulation section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at VREFIN/VREFOUT is typically 50 μV/V; see Figure 7.
The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage over varying temperature. The drift is calculated using the box method described by Equation 3:
where:
VREF_MAX = maximum reference voltage observed within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed within temperature range TRANGE.
VREF = 2.5 V, target value for reference output voltage.
TRANGE = the characterized range from –40°C to 125°C (165°C range)
The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C. Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift results are summarized in Figure 3.
Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade the ac performance. The output noise spectrum at the VREFIN/VREFOUT pin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal reference noise impacts the DAC output noise when the internal reference is used.
Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 95. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4. Force and sense lines should be used for applications that require improved load regulation.
Long-term stability or aging refers to the change of the output voltage of a reference over a period of months or years. This effect lessens as time progresses. The typical drift value for the internal reference is listed in the Electrical Charateristics and measurement results are shown in Figure 5. This parameter is characterized by powering up multiple devices and measuring them at regular intervals.
Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C, cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by Equation 4:
where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at 25°C pre-temperature cycling.
VREF_POST = output voltage measured after the device cycles through the temperature range of –40°C to
aaa 125°C, and returns to 25°C.
VREF_NOM = 2.5 V, target value for reference output voltage.
Output noise spectral density at the VOUT-n pin versus frequency is depicted in Figure 45 and Figure 46 for full-scale, mid-scale, and zero-scale input codes. The typical noise density for mid-scale code is 90 nV/√Hz at 1 kHz. High-frequency noise can be improved by filtering the reference noise. Integrated output noise between 0.1 Hz and 10 Hz is close to 2.5 µVPP (mid-scale), as shown in Figure 47.
The design features two independent outputs that can source and sink voltage and current over the standard industrial output ranges. The possible outputs of the design include: –24 mA to 24 mA, 4 mA–20 mA, 0 mA to 24 mA, 0 V to 5 V, 0 V to 10 V, –5 V to5 V, and –10 V to 10 V.
The design uses a DAC and a current-or-voltage output driver to create a discrete analog output design that can output either voltage or current from the same pin while focusing on high-accuracy specifications. The choice of the DAC8563 device takes advantage of its 16-bit resolution as well as its low typical offset error of 1 mV and gain error of 0.01% FSR. The choice of the XTR300 device is based on its strong dc performance, having a typical error of 400 µV and 0.04% FSR gain error. The XTR300 device allows a variety of both current and voltage outputs on the same pin while providing load monitoring and error status pins.
The power-on reset-to-midscale feature of the DAC8563 makes the bipolar output of the XTR300 power up at 0 V or 0 A. If using a unipolar output, the recommended device to achieve a system power-on output of 0 V, 0 A or 4 mA is the DAC8562 device.
A recommendation for minimizing the introduction of errors into the system is to use ±0.01% tolerance RG and RSET resistors. The bypass capacitors on AVDD, VREF, V+ and V– should have values between 100 nF and 10 µF. Smaller capacitors filter fast low-energy transients, whereas the large capacitors filter the slow high-energy transients. If there is an expectation of both types of signals in the system, the recommendation is to use a pair of small and large values as shown on the AVDD pin of the DAC8563 device in Figure 96.
When configured for voltage mode, the output of the instrumentation amplifier (IA), internal to the XTR300 device, is routed to the SET pin. The SET output provides feedback for the IA based on the IA input voltage. The feedback from the IA provides high-impedance remote sensing of the voltage at the output load. Using the output voltage can overcome errors from PCB traces and protection component impedances. The DAC provides a unipolar input voltage to the VIN pin of the XTR300 device. The XTR300 device offsets the VDAC range by a negative VREF and amplifies the difference by a value set by the RG and RSET resistors, as shown in Equation 5.
When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the RSET resistor from the SET pin to VREF to apply the offset and obtain the transfer function shown in Equation 6.
The desired output ranges for VDAC and VREF voltages determine the RSET and RG resistor values, calculated using Equation 7 and Equation 8. The system design requires a VDAC voltage range of 0.04 V to 4.96 V in order to operate the DAC8563 in the specified linear output range from codes 512 to 65 024.
IMON and IAOUT accomplish load monitoring. The sizing of RIMON and RIA determine the monitoring output voltage across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load current IDRV.
For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).
Figure 97 shows the transfer function for the bipolar ±10 V voltage range. This design also supports output voltage ranges of 0–5 V, 0–10 V and ±5 V. Figure 98 shows the transfer function for the unipolar 0–24 mA current range. This design also supports output current ranges of ±24 mA and 4 mA–20 mA.
The DAC8562 is designed to be operate from a single power supply providing a maximum output range of AVDD volts. However, the DAC can be placed in the configuration shown in Figure 99 in order to be designed into bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from ±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference enabled and the DAC8562 internal gain set to 2, however, an external 2.5-V reference could also be used (with DAC8562 internal gain set to 2).
The transfer function shown in Equation 5 can be used to calculate the output voltage as a function of the DAC code, reference voltage and resistor ratio:
where:
DIN = decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for DAC8562 (16 bit).
VREFOUT = reference output voltage with the internal reference enabled from the DAC VREFIN/VREFOUT pin
G = ratio of the resistors
An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and VREFOUT = 2.5 V:
In this example, the range is set to ±10 V by using a resistor ratio of four, VREFOUT of 2.5 V, and DAC8562 internal gain of 2. The resistor sizes must be selected keeping in mind the current sink or source capability of the DAC8562 internal reference. Using larger resistor values, for example, R = 10 kΩ or larger, is recommended. The op amp is selectable depending on the requirements of the system.
The DAC8562EVM and DAC7562EVM boards have the option to evaluate the bipolar output application by installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or DAC7562EVM product folder.
Figure 100 shows a serial interface between the DAC756x, DAC816x, or DAC856x device and a typical MSP430 USI port such as the one found on the MSP430F2013. The port is configured in SPI master mode by setting bits 3, 5, 6, and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means of SPI communication with minimal software overhead. The serial clock polarity, source, and speed are controlled by settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-programmable pin on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the DAC756x, DAC816x, or DAC856x device, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P1.4 is taken high following the completion of the third write cycle.
Figure 101 shows an interface between the DAC756x, DAC816x, or DAC856x device and any TMS320 series DSP from Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out on the rising edge of the serial clock and are clocked into the DAC756x, DAC816x, or DAC856x device on the falling edge of the SCLK signal.
Figure 102 shows a serial interface between the DAC756x, DAC816x, or DAC856x device and the OMAP-L138 processor. The transmit clock CLKx0 of the L138 drives SCLK of the DAC756x, DAC816x, or DAC856x device, and the data transmit (Dx0) output drives the serial data line of the DAC. The SYNC signal is derived from the frame sync transmit (FSx0) line, similar to the TMS320 interface.
These devices can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to AVDD should be well-regulated and low-noise. In order to further minimize noise from the power supplies, a strong recommendation is to include a pair of 100-pF and 1-nF capacitors and a 0.1-μF to 1-μF bypass capacitor. The current consumption of the AVDD pin, the short-circuit current limit, and the load current for these devices are listed in the Electrical Characteristics table. Choose the power supplies for these devices to meet the aforementioned current requirements.
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC756x, DAC816x, and DAC856x devices offer single-supply operation, and are often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. As a result of the single ground pin of the DAC756x, DAC816x, and DAC856x devices, all return currents (including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be well-regulated and low noise. Switching power supplies and dc-dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a pair of 100-pF to 1-nF capacitors and a 0.1-µF to 1-µF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a pi filter made up of inductors and capacitors – all designed essentially to provide low-pass filtering for the supply and remove the high-frequency noise.
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
DAC7562 | Click here | Click here | Click here | Click here | Click here |
DAC7563 | Click here | Click here | Click here | Click here | Click here |
DAC8162 | Click here | Click here | Click here | Click here | Click here |
DAC8163 | Click here | Click here | Click here | Click here | Click here |
DAC8562 | Click here | Click here | Click here | Click here | Click here |
DAC8563 | Click here | Click here | Click here | Click here | Click here |
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
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