The DLP160AP digital micromirror device (DMD) is a digitally controlled micro-opto-electromechanical system (MOEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP160AP DMD displays a crisp and high-quality image or video. DLP160AP is part of the chipset comprising the DLP160AP DMD and DLPC3420 controller. This chipset is also supported by the DLPA2000 or DLPA2005 PMIC/LED driver. The compact physical size of the DLP160AP is well-suited for portable equipment where small form factor and low power is important. The compact DLP160AP DMD coupled with the controller and PMIC/LED driver provides a complete system solution that enables small form factor, low power, and high image quality displays.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
DLP160AP | FQT (35) | 13.39 mm × 4.97 mm × 3.18 mm |
Changes from Revision B (May 2022) to Revision C (July 2023)
Changes from Revision A (November 2021) to Revision B (May 2022)
Changes from Revision * (November 2021) to Revision A (January 2022)
PIN(1) | PACKAGE NET LENGTH (mm)(2) | |||||
---|---|---|---|---|---|---|
NAME | NO. | TYPE | SIGNAL | DATA RATE | DESCRIPTION | |
DATA INPUTS | ||||||
D_N(0) | A2 | I | SubLVDS | Double | Data, negative | 1.91 |
D_N(1) | A4 | I | SubLVDS | Double | Data, negative | 3.6 |
D_N(2) | D4 | I | SubLVDS | Double | Data, negative | 3.28 |
D_N(3) | E2 | I | SubLVDS | Double | Data, negative | 1.67 |
D_P(0) | A3 | I | SubLVDS | Double | Data, positive | 2.03 |
D_P(1) | B4 | I | SubLVDS | Double | Data, positive | 3.7 |
D_P(2) | E4 | I | SubLVDS | Double | Data, positive | 3.39 |
D_P(3) | E3 | I | SubLVDS | Double | Data, positive | 1.77 |
DCLK_N | C3 | I | SubLVDS | Double | Clock, negative | 2.29 |
DCLK_P | C4 | I | SubLVDS | Double | Clock, positive | 2.4 |
CONTROL INPUTS | ||||||
LS_WDATA | C12 | I | LPSDR | Single | Write data for low-speed interface | 1.55 |
LS_CLK | C13 | I | LPSDR | Single | Clock for low-speed interface | 1.65 |
DMD_DEN_ARSTZ | D12 | I | LPSDR | Single | Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. | 1.57 |
LS_RDATA | D13 | O | LPSDR | Single | 1.43 | |
POWER | ||||||
VBIAS(3) | A13 | Power | Supply voltage for positive bias level at micromirrors | |||
VOFFSET(3) | E13 | Power | Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes. Supply voltage for offset level at micromirrors. | |||
VRESET(3) | A14 | Power | Supply voltage for negative reset level at micromirrors. | |||
VDD | B12 | Power | Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs. Supply voltage for normal high level at micromirror address electrodes. | |||
VDD | B14 | Power | ||||
VDD | C1 | Power | ||||
VDD | C14 | Power | ||||
VDD | C2 | Power | ||||
VDD | E14 | Power | ||||
VDDI | B1 | Power | Supply voltage for SubLVDS receivers. | |||
VDDI | D1 | Power | ||||
VSS | A1 | Ground | Common return. Ground for all power. | |||
VSS | A12 | Ground | ||||
VSS | B13 | Ground | ||||
VSS | B2 | Ground | ||||
VSS | B3 | Ground | ||||
VSS | D14 | Ground | ||||
VSS | D2 | Ground | ||||
VSS | D3 | Ground | ||||
VSS | E1 | Ground | ||||
VSS | E12 | Ground |
NUMBER | SYSTEM BOARD | ||
---|---|---|---|
A5 | Do not connect | ||
A6 | Do not connect | ||
A7 | Do not connect | ||
A8 | Do not connect | ||
A9 | Do not connect | ||
A10 | Do not connect | ||
A11 | Do not connect |