The DRV201 device is an advanced voice coil motor driver for camera auto focus. It has an integrated D/A converter for setting the VCM current. VCM current is controlled with a fixed frequency PWM controller or a linear mode driver. Current generation can be selected via I2C register. The DRV201 device has an integrated sense resistor for current regulation and the current can be controlled through I2C.
When changing the current in the VCM, the lens ringing is compensated with an advanced ringing compensation function. Ringing compensation reduces the needed time for auto focus significantly. The device also has VCM short and open protection functions.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV201 | DSBGA (6) | 0.80 mm × 1.48 mm |
PICOSTAR (6) | 0.80 mm × 1.48 mm |
Changes from B Revision (November 2013) to C Revision
Changes from A Revision (June 2012) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VBAT | 2A | P | Power |
GND | 1A | P | Ground |
I_SOURCE | 2B | O | Voice coil positive terminal |
I_SINK | 1B | O | Voice coil negative terminal |
SCL | 2C | I | I2C serial interface clock input |
SDA | 1C | I/O | I2C serial interface data input/output (open drain) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VBAT, ISOURCE, ISINK pin voltage(2) | –0.3 | 5.5 | V | |
Voltage at SDA, SCL | –0.3 | 3.6 | V | |
Continuous total power dissipation | Internally limited | |||
TJ | Operating junction temperature | –40 | 125 | °C |
TA | Operating ambient temperature | –40 | 85 | °C |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±4000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VBAT - Supply voltage | 2.5 | 3.7 | 4.8 | V | |
Voltage Range - SDA and SCL | –0.1 | 3.3 | 3.6 | V | |
TJ - Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DRV201 | UNIT | ||
---|---|---|---|---|
YFM (PICOSTAR) | YMB (DSBGA) | |||
6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 130.6 | 116.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.4 | 1.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 37 | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 5.2 | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 37 | 22.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT VOLTAGE | |||||||
VBAT | Input supply voltage | 2.5 | 3.7 | 4.8 | V | ||
VUVLO | Undervoltage lockout threshold | VBAT rising | 2.2 | V | |||
VBAT falling | 2 | ||||||
VHYS | Undervoltage lockout hysteresis | 50 | 100 | 250 | mV | ||
INPUT CURRENT | |||||||
ISHUTDOWN | Input supply current shutdown, includes switch leakage currents | MAX: VBAT = 4.4 V | 0.15 | 1 | µA | ||
ISTANDBY | Input supply current standby, includes switch leakage currents | MAX: VBAT = 4.4 V | 120 | 200 | µA | ||
STARTUP, MODE TRANSITIONS, AND SHUTDOWN | |||||||
t1 | Shutdown to standby | 100 | µs | ||||
t2 | Standby to active | 100 | µs | ||||
t3 | Active to standby | 100 | µs | ||||
t4 | Shutdown time | Active or standby to shutdown | 0.5 | 1 | ms | ||
VCM DRIVER STAGE | |||||||
IRES | Resolution | 10 | bits | ||||
Relative accuracy | –10 | 10 | LSB | ||||
Differential nonlinearity | –1 | 1 | |||||
Zero code error | 0 | mA | |||||
Offset error | At code 32 | 3 | mA | ||||
Gain error | ±3 | % of FSR | |||||
Gain error drift | 0.3 | 0.4 | %/°C | ||||
Offset error drift | 0.3 | 0.5 | %/°C | ||||
IMAX | Maximum output current | 102.3 | mA | ||||
ILIMIT | Average VCM current limit | See (1) | 110 | 160 | 240 | mA | |
IDETCODE | Minimum VCM code for OPEN and SHORT detection | See (2) | 256 | mA | |||
fSW | Switching frequency | Selectable through CONTROL register | 0.5 | 4 | MHz | ||
VDRP | Internal dropout | See (3) | 0.4 | V | |||
LVCM | VCM inductance | 30 | 150 | µH | |||
RVCM | VCM resistance | 11 | 22 | Ω | |||
LENS MOVEMENT CONTROL | |||||||
tset1 | Lens settling time | ±10% error band | 2/fVCM | ms | |||
tset2 | Lens settling time | ±10% error band | 1/fVCM | ms | |||
fVCM | VCM resonance frequency | 50 | 150 | Hz | |||
VCM resonance frequency tolerance | When 1/fVCM compensation is used | –10% | 10% | ||||
When 2/fVCM compensation is used | –30% | 30% | |||||
LOGIC I/Os (SDA AND SCL) | |||||||
IIN | Input leakage current | V = 1.8 V, SCL | –4.25 | 4.25 | µA | ||
V = 1.8 V, SDA | –1 | 1 | |||||
RPullUp | I2C pull-up resistors | SDA and SCL pins | 4.7 | kΩ | |||
VIH | Input high level | See (4) | 1.17 | 3.6 | V | ||
VIL | Input low level | See (5) | 0 | 0.63 | V | ||
tTIMEOUT | SCL timeout for shutdown detection | 0.5 | 1 | ms | |||
RPD | Pull down resistor at SCL line | 500 | kΩ | ||||
fSCL | I2C clock frequency | 400 | kHz | ||||
INTERNALOSCILLATOR | |||||||
fOSC | Internal oscillator | 20°C ≤ TA ≤ 70°C | –3% | 3% | |||
Frequency accuracy | -40°C ≤ TA ≤ 85°C | –5% | 5% | ||||
THERMAL SHUTDOWN | |||||||
TTRIP | Thermal shutdown trip point | 140 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(SCL) | Serial clock frequency | 100 | 400 | kHz | ||
tBUF | Bus Free Time Between Stop and Start Condition | SCL = 100 KHz | 4.7 | µs | ||
SCL = 400 KHz | 1.3 | |||||
tSP | Tolerable spike width on bus | SCL = 100 KHz | 50 | ns | ||
SCL = 400 KHz | ||||||
tLOW | SCL low time | SCL = 100 KHz | 4.7 | µs | ||
SCL = 400 KHz | 1.3 | |||||
tHIGH | SCL high time | SCL = 100 KHz | 4 | µs | ||
SCL = 400 KHz | 600 | ns | ||||
tS(DAT) | SDA → SCL setup time | SCL = 100 KHz | 250 | ns | ||
SCL = 400 KHz | 100 | |||||
tS(STA) | Start condition setup time | SCL = 100 KHz | 4.7 | µs | ||
SCL = 400 KHz | 600 | ns | ||||
tS(STO) | Stop condition setup time | SCL = 100 KHz | 4 | µs | ||
SCL = 400 KHz | 600 | ns | ||||
tH(DAT) | SDA → SCL hold time | SCL = 100 KHz | 0 | 3.45 | µs | |
SCL = 400 KHz | 0 | 0.9 | ||||
tH(STA) | Start condition hold time | SCL = 100 KHz | 4 | µs | ||
SCL = 400 KHz | 600 | ns | ||||
tr(SCL) | Rise time of SCL Signal | SCL = 100 KHz | 1000 | ns | ||
SCL = 400 KHz | 300 | |||||
tf(SCL) | Fall time of SCL Signal | SCL = 100 KHz | 300 | ns | ||
SCL = 400 KHz | 300 | |||||
tr(SDA) | Rise time of SDA Signal | SCL = 100 KHz | 1000 | ns | ||
SCL = 400 KHz | 300 | |||||
tf(SDA) | Rise time of SDA Signal | SCL = 100 KHz | 300 | ns | ||
SCL = 400 KHz | 300 |
VBAT = 3.7 V | ||
VBAT = 3.7 V | ||
VBAT = 3.7 V | ||
VBAT = 3.7 V | ||
The DRV201 device is intended for high performance autofocus in camera modules. The device is used to control the current in the voice coil motor (VCM). The current in the VCM generates a magnetic field which forces the lens stack connected to a spring to move. The VCM current and thus the lens position can be controlled via the I2C interface and an auto focus function can be implemented.
The device connects to a video processor or image sensor through a standard I2C interface which supports up to 400-kbit/s data rate. The digital interface supports IO levels from 1.8 V to 3.3 V. All pins have 4-kV HBM ESD rating.
When SCL is low for at least 0.5 ms, the device enters SHUTDOWN mode. If SCL goes from low to high the driver enters STANDBY mode in less than 100 μs and default register values are set as shown in Figure 5. ACTIVE mode is entered whenever the VCM_CURRENT register is set to something else than zero.
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT register is changed. This enables a fast autofocus algorithm and pleasant user experience.
Current in the VCM can be generated with a linear or PWM control. In linear mode the high side PMOS is configured as a current source and current is set by the VCM_CURRENT control register. In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between VBAT and GND through the high side PMOS and then released to a freewheeling mode through the sense resistor and low side NMOS. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is selected from MODE register bit PWM/LIN.
In linear mode the output PMOS is configured to a high side current source and current can be controlled from a VCM_CURRENT registers.
In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between VBAT and GND through the high side PMOS and then released to a freewheeling mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-Ω sense resistor which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT register is changed. This enables a fast auto focus algorithm and pleasant user experience.
Ringing compensation is dependent on the VCM resonance frequency, and this can be controlled via VCM_FREQ register (07h) from 50 Hz up 150 Hz. Table 1 shows the VCM_FREQ register setting for each resonance frequency in 1-Hz steps. If more accurate resonance frequency is available, the control value can be calculated with Equation 1.
Ringing compensation is designed in a way that it can tolerate ±30% frequency variation in the VCM resonance frequency when 2/fVCM compensation is used and ±10% variation with 1/fVCM so only statistical data from the VCM is needed in production.
VCM RESONANCE FREQUENCY [Hz] | VCM_FREQ[7:0] (07h) | VCM RESONANCE FREQUENCY [Hz] | VCM_FREQ[7:0] (07h) | VCM RESONANCE FREQUENCY [Hz] | VCM_FREQ[7:0] (07h) | |||
---|---|---|---|---|---|---|---|---|
DEC | BIN | DEC | BIN | DEC | BIN | |||
50 | 0 | 0 | 84 | 154 | 10011010 | 118 | 220 | 11011100 |
51 | 7 | 111 | 85 | 157 | 10011101 | 119 | 222 | 11011110 |
52 | 14 | 1110 | 86 | 160 | 10100000 | 120 | 223 | 11011111 |
53 | 21 | 10101 | 87 | 162 | 10100010 | 121 | 224 | 11100000 |
54 | 27 | 11011 | 88 | 165 | 10100101 | 122 | 226 | 11100010 |
55 | 34 | 100010 | 89 | 167 | 10100111 | 123 | 227 | 11100011 |
56 | 40 | 101000 | 90 | 170 | 10101010 | 124 | 228 | 11100100 |
57 | 46 | 101110 | 91 | 172 | 10101100 | 125 | 229 | 11100101 |
58 | 52 | 110100 | 92 | 174 | 10101110 | 126 | 231 | 11100111 |
59 | 58 | 111010 | 93 | 177 | 10110001 | 127 | 232 | 11101000 |
60 | 63 | 111111 | 94 | 179 | 10110011 | 128 | 233 | 11101001 |
61 | 68 | 1000100 | 95 | 181 | 10110101 | 129 | 234 | 11101010 |
62 | 73 | 1001001 | 96 | 183 | 10110111 | 130 | 235 | 11101011 |
63 | 78 | 1001110 | 97 | 185 | 10111001 | 131 | 236 | 11101100 |
64 | 83 | 1010011 | 98 | 187 | 10111011 | 132 | 238 | 11101110 |
65 | 88 | 1011000 | 99 | 189 | 10111101 | 133 | 239 | 11101111 |
66 | 92 | 1011100 | 100 | 191 | 10111111 | 134 | 240 | 11110000 |
67 | 96 | 1100000 | 101 | 193 | 11000001 | 135 | 241 | 11110001 |
68 | 101 | 1100101 | 102 | 195 | 11000011 | 136 | 242 | 11110010 |
69 | 105 | 1101001 | 103 | 197 | 11000101 | 137 | 243 | 11110011 |
70 | 109 | 1101101 | 104 | 198 | 11000110 | 138 | 244 | 11110100 |
71 | 113 | 1110001 | 105 | 200 | 11001000 | 139 | 245 | 11110101 |
72 | 116 | 1110100 | 106 | 202 | 11001010 | 140 | 246 | 11110110 |
73 | 120 | 1111000 | 107 | 204 | 11001100 | 141 | 247 | 11110111 |
74 | 124 | 1111100 | 108 | 205 | 11001101 | 142 | 248 | 11111000 |
75 | 127 | 1111111 | 109 | 207 | 11001111 | 143 | 249 | 11111001 |
76 | 130 | 10000010 | 110 | 208 | 11010000 | 144 | 250 | 11111010 |
77 | 134 | 10000110 | 111 | 210 | 11010010 | 145 | 251 | 11111011 |
78 | 137 | 10001001 | 112 | 212 | 11010100 | 146 | 251 | 11111011 |
79 | 140 | 10001100 | 113 | 213 | 11010101 | 147 | 252 | 11111100 |
80 | 143 | 10001111 | 114 | 215 | 11010111 | 148 | 253 | 11111101 |
81 | 146 | 10010010 | 115 | 216 | 11011000 | 149 | 254 | 11111110 |
82 | 149 | 10010101 | 116 | 217 | 11011001 | 150 | 255 | 11111111 |
83 | 152 | 10011000 | 117 | 219 | 11011011 | — | — | — |
If the driver detects SCL has a DC level below 0.63 V for duration of at least 0.5 ms, the driver will enter SHUTDOWN mode. This is the lowest power mode of operation. The driver will remain in SHUTDOWN for as long as SCL pin remain low.
If SCL goes from low to high the driver enters STANDBY mode and sets the default register values. In this mode registers can be written to through the I2C interface. Device will be in STANDBY mode when VCM_CURRENT register is set to zero. From ACTIVE mode the device will enter STANDBY if the SW_RST bit of the CONTROL register is set. In this case all registers will be reset to default values.
STANDBY mode is entered from ACTIVE mode if any of the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). When STANDBY mode is entered due to a fault condition current register is cleared.
The device is in ACTIVE mode whenever the VCM_CURRENT control is set to something else than zero through the I2C interface. In ACTIVE mode VCM driver output stage is enabled all the time resulting in higher power consumption. The device remains in ACTIVE mode until the SW_RST bit in the CONTROL register is set, SCL is pulled low for duration of 0.5 ms, VCM_CURRENT control is set to zero, or any of the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). If ACTIVE mode is entered after fault the status register is automatically cleared.
The I2C bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission.
The DRV201 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.
DRV201 supports four different read and two different write operations: single read from a defined location, single read from a current location, sequential read starting from a defined location, sequential read from current location, single write to a defined location, sequential write starting from a defined location. All different read and write operations are described below.
Figure 6 shows the format of a single write to a defined register. First, the master issues a start condition followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201 sets the I2C register to a defined value and the master writes the eight-bit data value across the bus. Upon receiving a third acknowledge, DRV201 auto increments the internal I2C register number by one and the master issues a stop condition. This action concludes the register write.
Figure 7 shows the format of a single read from a defined location. First, the master issues a start condition followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201 sets the internal I2C register number to a defined value. Then the master issues a repeat start condition and a seven-bit I2C address followed by a one to conduct a read operation. Upon receiving a third acknowledge, the master releases the bus to the DRV201. The DRV201 then writes the eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a stop condition. This action concludes the register read.
Figure 8 shows the single read from the current location. If the read command is issued without defining the register number first, DRV201 writes out the data from the current register from the device memory.
Sequential read and write allows simple and fast access to DRV201 registers. Figure 9 shows sequential read from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments the register number and writes the data from the next register.
Figure 10 shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments it’s register by one and the master can write to the next register.
If read is started without writing the register value first, DRV201 writes out data from the current location. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments the I2C register and writes out the data. This continues until the master issues a stop condition. This is shown in Figure 11.
Data transmission is initiated with a start bit from the controller as shown in Figure 12. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. SDA data is latched by DRV201 on the rising edge of the SCL line. If the appropriate device address bits are set for the device, DRV201 issues the ACK by pulling the SDA line low on the next falling edge after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.
Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. Reference Figure 13.
REGISTER | ADDRESS (HEX) | NAME | DEFAULT VALUE |
DESCRIPTION |
---|---|---|---|---|
1 | 01 | not used | ||
2 | 02 | CONTROL | 0000 0010 | Control register |
3 | 03 | VCM_CURRENT_MSB | 0000 0000 | Voice coil motor MSB current control |
4 | 04 | VCM_CURRENT_LSB | 0000 0000 | Voice coil motor LSB current control |
5 | 05 | STATUS | 0000 0000 | Status register |
6 | 06 | MODE | 0000 0000 | Mode register |
7 | 07 | VCM_FREQ | 1000 0011 | VCM resonance frequency |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | not used | not used | not used | not used | not used | not used | EN_RING | RESET |
READ/WRITE | R | R | R | R | R | R | R/W | R/W |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
RESET | Forced software reset (reset all registers to default values) and device goes into STANDBY. RESET bit is automatically cleared when written high. |
0 – inactive | |
1 – device goes to STANDBY | |
EN_RING | Enables ringing compensation. |
0 – disabled | |
1 – enabled |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | not used | not used | not used | not used | not used | not used | VCM_CURRENT[9:8] | |
READ/WRITE | R | R | R | R | R | R | R/W | |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
VCM_CURRENT[9:8] | VCM current control |
00 0000 0000b – 0 mA | |
00 0000 0001b – 0.1 mA | |
00 0000 0010b – 0.2 mA | |
… | |
11 1111 1110b – 102.2 mA | |
11 1111 1111b – 102.3 mA NOTE When setting the current in DRV201 both VCM_CURRENT_MSB and VCM_CURRENT_LSB registers have to be updated. DRV201 starts updates the current after LSB register write is completed. |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VCM_CURRENT[7:0] | |||||||
READ/WRITE | R/W | |||||||
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
VCM_CURRENT[7:0] | VCM current control |
00 0000 0000b – 0 mA | |
00 0000 0001b – 0.1 mA | |
00 0000 0010b – 0.2 mA | |
… | |
11 1111 1110b – 102.2 mA | |
11 1111 1111b – 102.3 mA NOTE When setting the current in DRV201 both VCM_CURRENT_MSB and VCM_CURRENT_LSB registers have to be updated. DRV201 starts updates the current after LSB register write is completed. |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | not used | not used | not used | TSD | VCMS | VCMO | UVLO | OVC |
READ/WRITE | R | R/WR | R | R | R | R | R | R |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
OVC | Over current detection |
UVLO | Undervoltage Lockout |
VCMO | Voice coil motor open detected |
VCMS | Voice coil motor short detected |
TSD | Thermal shutdown detected |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | not used | not used | not used | PWM_FREQ[2:0] | PWM/LIN | RING_MODE | ||
READ/WRITE | R | R | R | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
RING_MODE | Ringing compensation settling time |
0 – 2x(1/fVCM) | |
1 – 1x(1/fVCM) | |
PWM/LIN | Driver output stage in linear or PWM mode |
0 – PWM mode | |
1 – Linear mode | |
PWM_FREQ[2:0] | Output stage PWM switching frequency |
000 – 0.5 MHz | |
001 – 1 MHz | |
010 – N/A | |
011 – 2 MHz | |
100 – N/A | |
101 – 4.8 MHz | |
110 – 6.0 MHz | |
111 – 4 MHz |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VCM_FREQ[7:0] | |||||||
READ/WRITE | R/W | |||||||
RESET VALUE | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
FIELD NAME | BIT DEFINITION |
---|---|
VCM_FREQ[7:0] | VCM mechanical ringing frequency for the ringing compensation can be selected with the below formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to the nearest integer. |
Equation 1.
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Default VCM mechanical ringing frequency is 76.4 Hz. | |
Equation 2.
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