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  • DRV2625 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Built-In Library

    • SLOS879B April   2014  – September 2016 DRV2625

      PRODUCTION DATA.  

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  • DRV2625 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Built-In Library
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Setup for Graphs
      1. 7.1.1 Default Test Conditions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Support for ERM and LRA Actuators
      2. 8.3.2  Smart-Loop Architecture
        1. 8.3.2.1 Auto-Resonance Engine for LRA
        2. 8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA
        3. 8.3.2.3 Automatic Switch to Open-Loop for LRA
        4. 8.3.2.4 Automatic Overdrive and Braking
          1. 8.3.2.4.1 Startup Boost
          2. 8.3.2.4.2 Brake Factor
        5. 8.3.2.5 Automatic Level Calibration
          1. 8.3.2.5.1 Automatic Compensation for Resistive Losses
          2. 8.3.2.5.2 Automatic Back-EMF Normalization
          3. 8.3.2.5.3 Calibration Time Adjustment
          4. 8.3.2.5.4 Loop-Gain Control
          5. 8.3.2.5.5 Back-EMF Gain Control
        6. 8.3.2.6 Actuator Diagnostics
        7. 8.3.2.7 Automatic Re-Synchronization
      3. 8.3.3  Open-Loop Operation
        1. 8.3.3.1 Waveform Shape Selection for LRA
        2. 8.3.3.2 Automatic Braking in Open Loop
      4. 8.3.4  Flexible Front-End Interface
        1. 8.3.4.1 Internal Memory Interface
          1. 8.3.4.1.1 Library Parameterization
          2. 8.3.4.1.2 Playback Interval
          3. 8.3.4.1.3 Waveform Sequencer
        2. 8.3.4.2 Real-Time Playback (RTP) Interface
        3. 8.3.4.3 Process Trigger
      5. 8.3.5  Noise Gate Control
      6. 8.3.6  Edge Rate Control
      7. 8.3.7  Constant Vibration Strength
      8. 8.3.8  Battery Voltage Reporting
      9. 8.3.9  Ultra Low-Power Shutdown
      10. 8.3.10 Automatic Go-To-Stand-by (Low Power)
      11. 8.3.11 I2C Watchdog Timer
      12. 8.3.12 Device Protection
        1. 8.3.12.1 Thermal Sensor
        2. 8.3.12.2 Over-Current Protection
        3. 8.3.12.3 VDD UVLO Protection
        4. 8.3.12.4 Brownout Protection
      13. 8.3.13 POR
      14. 8.3.14 Silicon Revision Control
      15. 8.3.15 Support for LRA and ERM Actuators
      16. 8.3.16 Multi-Purpose Pin Functionality
        1. 8.3.16.1 Trigger-Pulse Functionality
        2. 8.3.16.2 Trigger-Level (Enable) Functionality
        3. 8.3.16.3 Interrupt Functionality
      17. 8.3.17 Automatic Transition to Standby State
      18. 8.3.18 Automatic Brake into Standby
      19. 8.3.19 Battery Monitoring and Power Preservation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
      2. 8.4.2 Operation With VDD < 2.5 V (Minimum VDD)
      3. 8.4.3 Operation With VDD > 6 V (Absolute Maximum VDD)
      4. 8.4.4 Operation in Shutdown State
      5. 8.4.5 Operation in STANDBY State
      6. 8.4.6 Operation in ACTIVE State
      7. 8.4.7 Changing Modes of Operation
    5. 8.5 Operation During Exceptional Conditions
      1. 8.5.1 Operation With No Actuator Attached
      2. 8.5.2 Operation With a Non-Moving Actuator Attached
      3. 8.5.3 Operation With a Short at REG Pin
      4. 8.5.4 Operation With a Short at OUT+, OUT-, or Both
    6. 8.6 Programming
      1. 8.6.1 Auto-Resonance Engine Programming for the LRA
        1. 8.6.1.1 Drive-Time Programming
        2. 8.6.1.2 Current-Dissipation Time Programming
        3. 8.6.1.3 Blanking Time Programming
        4. 8.6.1.4 Zero-Crossing Detect-Time Programming
      2. 8.6.2 Automatic-Level Calibration Programming
        1. 8.6.2.1 Rated Voltage Programming
        2. 8.6.2.2 Overdrive Voltage-Clamp Programming
      3. 8.6.3 I2C Interface
        1. 8.6.3.1 TI Haptic Broadcast Mode
        2. 8.6.3.2 I2C Communication Availability
        3. 8.6.3.3 General I2C Operation
        4. 8.6.3.4 Single-Byte and Multiple-Byte Transfers
        5. 8.6.3.5 Single-Byte Write
        6. 8.6.3.6 Multiple-Byte Write and Incremental Multiple-Byte Write
        7. 8.6.3.7 Single-Byte Read
        8. 8.6.3.8 Multiple-Byte Read
      4. 8.6.4 Programming for Open-Loop Operation
        1. 8.6.4.1 Programming for ERM Open-Loop Operation
        2. 8.6.4.2 Programming for LRA Open-Loop Operation
      5. 8.6.5 Programming for Closed-Loop Operation
      6. 8.6.6 Diagnostics Routine
      7. 8.6.7 Calibration Routine
      8. 8.6.8 Waveform Playback Programming
        1. 8.6.8.1 Data Formats for Waveform Playback
        2. 8.6.8.2 Open-Loop Mode
        3. 8.6.8.3 Closed-Loop Mode
      9. 8.6.9 Waveform Setup and Playback
        1. 8.6.9.1 Waveform Playback Using RTP Mode
        2. 8.6.9.2 Waveform Sequencer
        3. 8.6.9.3 Waveform Playback Triggers
          1. 8.6.9.3.1 Playback Trigger Without Automatic Brake into Standby
            1. 8.6.9.3.1.1 Playback Trigger With Automatic Brake into Standby (SimpleDrive)
    7. 8.7 Register Map
      1. 8.7.1  Address: 0x00
      2. 8.7.2  Address: 0x01
      3. 8.7.3  Address: 0x02
      4. 8.7.4  Address: 0x03
      5. 8.7.5  Address: 0x04
      6. 8.7.6  Address: 0x05
      7. 8.7.7  Address: 0x06
      8. 8.7.8  Address: 0x07
      9. 8.7.9  Address: 0x08
      10. 8.7.10 Address: 0x09
      11. 8.7.11 Address: 0x0A
      12. 8.7.12 Address: 0x0B
      13. 8.7.13 Address: 0x0C
      14. 8.7.14 Address: 0x0D
      15. 8.7.15 Address: 0x0E
      16. 8.7.16 Address: 0x0F
      17. 8.7.17 Address: 0x10
      18. 8.7.18 Address: 0x11
      19. 8.7.19 Address: 0x12
      20. 8.7.20 Address: 0x13
      21. 8.7.21 Address: 0x14
      22. 8.7.22 Address: 0x15
      23. 8.7.23 Address: 0x16
      24. 8.7.24 Address: 0x17
      25. 8.7.25 Address: 0x18
      26. 8.7.26 Address: 0x19
      27. 8.7.27 Address: 0x1A
      28. 8.7.28 Address: 0x1B
      29. 8.7.29 Address: 0x1C
      30. 8.7.30 Address: 0x1D
      31. 8.7.31 Address: 0x1F
      32. 8.7.32 Address: 0x20
      33. 8.7.33 Address: 0x21
      34. 8.7.34 Address: 0x22
      35. 8.7.35 Address: 0x23
      36. 8.7.36 Address: 0x24
      37. 8.7.37 Address: 0x25
      38. 8.7.38 Address: 0x26
      39. 8.7.39 Address: 0x27
      40. 8.7.40 Address: 0x28
      41. 8.7.41 Address: 0x29
      42. 8.7.42 Address: 0x2A
      43. 8.7.43 Address: 0x2C
      44. 8.7.44 Address: 0x2E
      45. 8.7.45 Address: 0x2F
      46. 8.7.46 Address: 0x30
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Actuator Selection
          1. 9.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)
          2. 9.2.2.1.2 Linear Resonance Actuators (LRA)
            1. 9.2.2.1.2.1 Auto-Resonance Engine for LRA
        2. 9.2.2.2 Capacitor Selection
        3. 9.2.2.3 Interface Selection
        4. 9.2.2.4 Power Supply Selection
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initialization Procedure
      2. 9.3.2 Typical Usage Examples
        1. 9.3.2.1 Play a Waveform or Waveform Sequence from the ROM Waveform Memory
        2. 9.3.2.2 Play a Real-Time Playback (RTP) Waveform
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Waveform Library Effects List
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slos879b_oa
  • slos879b_pm
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DATA SHEET

DRV2625 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Built-In Library

1 Features

  • Ultra Low-Power Shutdown Mode
  • Low-Power Standby State
  • Resistance-Based Actuator Diagnostics
  • SimpleDrive One-Wire Vibration Scheme
  • Automatic Resonance Tracking and Reporting
  • Automatic Overdrive and Braking
  • Automatic Level Calibration
  • Drive Compensation Over Battery Discharge
  • Configurable Battery Monitor with Power Preservation
  • Off-Resonance Driving with Auto-Braking
  • LRA Waveform Shape Selection
  • Licensed Immersion TouchSense® 2200
  • Built-In Library with Loopable Waveform Sequencer
  • Real-Time Playback (RTP) Mode
  • I2C-Controlled Digital Playback Engine
  • Hardware and Software Trigger Option
  • Automatic Transition to Standby with Auto-Brake
  • Optional Interrupt Pin
  • 1.8-V Compatible, VDD Tolerant Digital Interface (1)
(1)
(1) Patent pending control algorithm

2 Applications

  • Mobile Phones and Tablets
  • Fitness Bands and Wearable Devices
  • Remote Controls, Mice, and Peripheral Devices
  • Touch-Enabled Devices
  • Human-Machine Interfaces

3 Description

The DRV2625 device is a haptic driver that relies on a proprietary closed-loop architecture to deliver sharp, strong, and consistent haptic effects while optimizing power consumption.

The internal library and loopable waveform sequencer, together with the automatic overdrive and braking simplifies the process of generating crisp and optimum haptic effects, reducing the burden imposed into the processing unit.

The DRV2625 device features an automatic go-to-standby state and a battery preservation function to help reduce power consumption without user intervention. The NRST pin allows for a full shutdown state for additional power savings.

The waveform shape selection allows for sine-wave and square-wave drive to customize the haptic feel as well as the audible performance. Off-resonance driving with automatic braking simplifies the implementation of non-resonant haptic solutions.

Device Information(1)

DEVICE NAME PACKAGE BODY SIZE (MAX)
DRV2625 DSBGA (9) 1.498 mm × 1.361 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

DRV2625 Simplified_Schematic_slos893.gif

4 Revision History

Changes from A Revision (December 2015) to B Revision

  • Updated REV[3:0] from 2 to 3 Go
  • Changed Default of 0x00 Register Go
  • Changed Default of 0x07 Register Go
  • Changed Bits 7 and 6 of 0x0D Register Go
  • Changed the calculation value for the open loop LRA drive of register 0x2E from 'OL_LRA_PERIOD[9:0] × 24.39 µs' to 'OL_LRA_PERIOD[9:0] × 24.615 µs'Go

Changes from * Revision (December 2015) to A Revision

  • Changed data sheet from Product Preview to Production DataGo

5 Pin Configuration and Functions

YFF Package
9-Pin DSBGA
Top View
DRV2625 WCSPPackage_slos879.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VDD C2 P Supply input (2.7 V to 5.5 V). A 0.1-µF capacitor is required.
GND B3 P Supply ground
REG A2 O 1.8 V regulator output. A 0.1-µF capacitor is required
OUT- C3 O Negative haptic driver differential output
OUT+ A3 O Positive haptic driver differential output
SDA B1 I/O I2C data
SCL C1 I I2C clock
TRIG/INTZ A1 I/O

Multi-mode pin. Selectable as input trigger (pulse), input enable, or output interrupt. This pin has an internal pull-down.

If pin is not used, it should be connected to ground.
NRST B2 I Device reset pin (shutdown mode). If pin is not used, it should be connected to VDD (no internal pull-up or pull-down).

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Voltage VDD –0.3 6 V
Input voltage NRST –0.3 6 V
SDA –0.3 6 V
SCL –0.3 6 V
TRIG/INTZ –0.3 6 V
Operating free-air temperature range, TA –40 85 °C
Operating junction temperature range, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

MIN MAX UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –1500 1500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 2.7 5.5 V
RL Load impedance 8 Ω
CL Load capacitance 100 pF
ƒ(LRA) LRA frequency 45 300 Hz

6.4 Thermal Information

THERMAL METRIC(1) DRV2625 UNIT
DSBGA
9 PINS
RθJA Junction-to-ambient thermal resistance 107 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 18.1 °C/W
ψJT Junction-to-top characterization parameter 3.8 °C/W
ψJB Junction-to-board characterization parameter 18.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25 °C, VDD = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(REG) Voltage at the REG pin 1.84 V
IIL Digital low-level input current NRST, TRIG/INTZ, SDA, SCL
VDD = 5.5 V, VI = 0 V		 100 nA
IIH Digital high-level input current SDA, SCL
VDD = 5.5 V, VI = VDD		 0.1 µA
NRST
VDD = 5.5 V, VI = VDD 		1
TRIG/INTZ
VDD = 5.5 V, VI = VDD 		2.7 3.5
VIL Digital low-level input voltage NRST, TRIG/INTZ, SDA, SCL 0.4 V
VIH Digital high-level input voltage NRST, TRIG/INTZ, SDA, SCL 1.41 V
VOL Digital low-level output voltage TRIG/INTZ, SDA
3-mA sink current		 0.4 V
RDS(on) Drain-source on-state resistance (LS + HS) 0.75 Ω
I(SD) Shutdown current V(NRST) = 0 V 105 180 nA
I(STBY) Standby current V(NRST) = VDD
In stand-by mode		 1.55 2 µA
I(Q) Quiescent current V(NRST) = VDD
In idle mode - no signal		 2.5 mA
ZO(SD) Output impedance in shutdown OUT+ to GND, OUT– to GND 15 kΩ
ZO(STBY) Output impedance in standby OUT+ to GND, OUT– to GND 15 kΩ
ZLOAD(th) Load impedance threshold for over-current detection OUT+ to GND, OUT– to GND 4 Ω

6.6 Timing Requirements

TA = 25 °C, VDD = 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
ƒ(SCL) Frequency at the SCL pin with no wait states 400 kHz
tw(H) Pulse duration, SCL high 0.6 µs
tw(L) Pulse duration, SCL low 1.3 µs
tsu(1) Setup time, SDA to SCL 100 ns
th(1) Hold time, SCL to SDA 10 ns
t(BUF) Bus free time between stop and start condition 1.3 µs
tsu(2) Setup time, SCL to start condition 0.6 µs
th(2) Hold time, start condition to SCL 0.6 µs
tsu(3) Setup time, SCL to stop condition 0.6 µs

6.7 Switching Characteristics

TA = 25 °C, VDD = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(on) Device startup time from shutdown standby 1 ms
t(start) Waveform startup time from trigger to output signal 1 ms
fO(PWM) PWM output frequency (in OUT+ and OUT-) 20.5 kHz
DRV2625 i2c_timing_slos879.gif Figure 1. SCL and SDA Timing
DRV2625 i2c_start_stop_timing_slos879.gif Figure 2. Timing for Start and Stop Conditions

6.8 Typical Characteristics

DRV2625 Fig12_Standby_Current_vs_VDD.png
Figure 3. Standby Current vs Supply Voltage
DRV2625 Fig1_ERM_Click_Ext_Pulse_Trigger.png
VDD = 3.6 V
Figure 5. ERM Click (Open-Loop) with External Pulse-Trigger
DRV2625 Fig3_ERM_Click_Bounce_Int_Trigger.png
VDD = 3.6 V
Figure 7. ERM Click-Bounce (Open-Loop) with Internal Trigger
DRV2625 Fig5_ERM_Buzz_RTP_Ext_Pulse.png
VDD = 3.6 V
Figure 9. ERM RTP Buzz (Closed-Loop) with Pulse-Trigger
DRV2625 Fig9_LRA_Squarewave_Click.png
VDD = 3.6 V
Figure 11. LRA Squarewave Click (Open-Loop) with Automatic Braking
DRV2625 Fig13_RTP_CL_Sinewave.png
VDD = 3.6 V
Figure 13. LRA SimpleDrive with Closed-Loop
DRV2625 Fig6_Startup_Latency_for_ERM_and_LRA.png
VDD = 3.6 V
Figure 4. Startup Latency for ERM and LRA
DRV2625 Fig2_LRA_Strong_Click_Internal.png
VDD = 3.6 V
Figure 6. LRA Strong Click (Closed-Loop) with External Level-Trigger
DRV2625 Fig4_LRA_Transition_Click_1_Internal.png
VDD = 3.6 V
Figure 8. LRA Transition Click (Closed-Loop) with Internal Trigger
DRV2625 Fig8_LRA_Sinewave_Click.png
VDD = 3.6 V
Figure 10. LRA Sinewave Click (Open-Loop) with Automatic Braking
DRV2625 Fig10_ERM_OL_Click_with_Autobrake.png
VDD = 3.6 V
Figure 12. ERM Click (Open-Loop) with Automatic Braking
DRV2625 Fig14_RTP_Sinewave.png
VDD = 3.6 V
Figure 14. LRA SimpleDrive with Sinewave

 
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