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DRV8376Three-Phase Integrated FET Motor Driver
SLVSHD4A
October 2024 – March 2025
DRV8376
PRODUCTION DATA
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DRV8376Three-Phase Integrated FET Motor Driver
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
SPI Timing Requirements
6.7
SPI Slave Mode Timings
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Output Stage
7.3.2
Control Modes
7.3.2.1
6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
7.3.2.2
3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD or to GVDD with RMODE)
7.3.3
Device Interface Modes
7.3.3.1
Serial Peripheral Interface (SPI)
7.3.3.2
Hardware Interface
7.3.4
AVDD and GVDD Linear Voltage Regulator
7.3.5
Charge Pump
7.3.6
Slew Rate Control
7.3.7
Cross Conduction (Dead Time)
7.3.8
Propagation Delay
7.3.9
Pin Diagrams
7.3.9.1
Logic Level Input Pin (Internal Pulldown)
7.3.9.2
Logic Level Input Pin (Internal Pullup)
7.3.9.3
Open Drain Pin
7.3.9.4
Push Pull Pin
7.3.9.5
Four Level Input Pin
7.3.10
Current Sense Amplifiers
7.3.10.1
Current Sense Amplifier Operation
7.3.11
Active Demagnetization
7.3.11.1
Automatic Synchronous Rectification Mode (ASR Mode)
7.3.11.1.1
Automatic Synchronous Rectification in Commutation
7.3.11.1.2
Automatic Synchronous Rectification in PWM Mode
7.3.11.2
Automatic Asynchronous Rectification Mode (AAR Mode)
7.3.12
Cycle-by-Cycle Current Limit
7.3.12.1
Cycle by Cycle Current Limit with 100% Duty Cycle Input
7.3.13
Protections
7.3.13.1
VM Supply Undervoltage Lockout (RESET)
7.3.13.2
AVDD Undervoltage Protection (AVDD_UV)
7.3.13.3
GVDD Undervoltage Lockout (GVDD_UV)
7.3.13.4
VCP Charge Pump Undervoltage Lockout (CPUV)
7.3.13.5
Overvoltage Protections (OV)
7.3.13.6
Overcurrent Protection (OCP)
7.3.13.6.1
OCP Latched Shutdown (OCP_MODE = 00b)
7.3.13.6.2
OCP Automatic Retry (OCP_MODE = 01b)
7.3.13.6.3
OCP Report Only (OCP_MODE = 10b)
7.3.13.6.4
OCP Disabled (OCP_MODE = 11b)
7.3.13.7
Thermal Warning (OTW)
7.3.13.8
Thermal Shutdown (OTS)
7.4
Device Functional Modes
7.4.1
Functional Modes
7.4.1.1
Sleep Mode
7.4.1.2
Operating Mode
7.4.1.3
Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
7.4.2
DRVOFF Functionality
7.5
SPI Communication
7.5.1
Programming
7.5.1.1
SPI Format
8
Register Map
8.1
STATUS Registers
8.2
CONTROL Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Three-Phase Brushless-DC Motor Control
9.2.1.1
Detailed Design Procedure
9.2.1.1.1
Motor Voltage
9.2.1.1.2
Using Active Demagnetization
9.2.1.1.3
Current Limit Implementation
9.2.1.1.4
Current Sensing and Output Filtering
9.2.1.1.5
Power Dissipation and Junction Temperature Losses
9.2.1.2
Application Curves
9.3
Power Supply Recommendations
9.3.1
Bulk Capacitance
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
9.4.3
Thermal Considerations
9.4.3.1
Power Dissipation
10
Device and Documentation Support
10.1
Documentation Support
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
NLG|28
MPQF811A
Thermal pad, mechanical data (Package|Pins)
NLG|28
QFND825
Orderable Information
slvshd4a_oa
slvshd4a_pm
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Data Sheet
DRV8376
Three-Phase Integrated FET Motor Driver
1
Features
Three-phase BLDC motor driver
Supports 48V systems
Supports up to 100kHz PWM frequency
Active Demagnetization to reduce power losses
Cycle-by-cycle current limit to limit phase current
4.5V to 65V operating voltage (70V abs max)
High output current capability: 4.5A Peak
Low MOSFET on-state resistance
400mΩ R
DS(ON)
(HS + LS) at T
A
= 25°C
Reduced switching loss with 1.1V/ns slew rate and reverse recovery loss minimization technique
Adjustable slew rate options
Low audible noise and ease of motor control with ultra-low dead time < 200ns, and propagation delay < 100ns
Low-power sleep mode
1.5µA typical at V
VM
= 24V, T
A
= 25°C
Multiple control interface options
6x PWM control interface
3x PWM control interface
Does not require external current sense resistors, built-in current sensing
Flexible device configuration options
DRV8376S: 5MHz 16-bit SPI for device configuration and fault status
DRV8376H: Hardware pin-based configuration
Supports 1.8V, 3.3V, and 5V logic inputs
Built-in 3.3V (5%), 30mA LDO regulator
Built-in 5V (5%), 30mA LDO regulator
Integrated protection features
Supply under voltage lockout (UVLO)
Charge pump under voltage (CPUV)
Overcurrent protection (OCP)
Thermal warning and shutdown (OTW/OTSD)
Fault condition indication pin (nFAULT)
Optional fault diagnostics over SPI
2
Applications
Brushless-DC (BLDC) Motor Modules
HVAC motors
Office automation machines
Factory automation and robotics
Wireless antenna motor
Drones