DRV8806 Quad Serial Interface Low-Side Driver IC
- SLVSBA3C June 2012 – December 2015 DRV8806
  
  PRODUCTION DATA.

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DATA SHEET

DRV8806 Quad Serial Interface Low-Side Driver IC

1 Features

4-Channel Protected Low-Side Driver
- Four NMOS FETs With Overcurrent Protection
- Integrated Inductive Clamp Diodes
- Serial Interface
- Open/Shorted Load Detection
2-A (Single Channel On)/1-A (All Channels On) Maximum Drive Current per Channel (at 25°C)
8.2-V to 40-V Operating Supply Voltage Range
Thermally-Enhanced Surface Mount Package

2 Applications

Relay Drivers
Unipolar Stepper Motor Drivers
Solenoid Drivers
General Low-Side Switch Applications

3 Description

The DRV8806 provides a 4-channel low-side driver with overcurrent protection. It has built-in diodes to clamp turnoff transients generated by inductive loads and can be used to drive unipolar stepper motors, DC motors, relays, solenoids, or other loads.

The DRV8806 can supply up to 2-A (single channel on) or 1-A (all channels on) continuous output current (with adequate PCB heatsinking at 25°C).

A serial interface is provided to control the output drivers. Fault status can be read through the serial interface. Multiple DRV8806 devices can be chained together to use a single serial interface.

Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature, and faults are indicated by a fault output pin.

The DRV8806 is available in a 16-pin HTSSOP package (Eco-friendly: RoHS & no Sb/Br).

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DRV8806	HTSSOP (16)	5.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

4 Revision History

Changes from B Revision (December 2013) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from A Revision (November 2013) to B Revision

Changed (OPEN-DRAIN to PUSH-PULL in the elec chara table section SDATAOUT OUTPUTGo
Added another row below V_OH - merge the first two columns together (V_OH and Output high voltage). The second row should have test condition "Io = 100 uA, VM = 8.2 V" and be specified as 2.5 V MINGo
Added two new rows, I_SRC and I_SNK in elec chara table, section SDATAOUT OUTPUTGo
Changed NO. 6 in Timing Requirements table Go
Added a sentence in second paragraph below Figure 2: A pullup resistor......1 kohm is recommended.Go

Changes from * Revision (June 2012) to A Revision

Added comment to Timing Requirements sectionGo
Changed Functional Block Diagram at SDATOUTGo
Changed Figure 6 at SDATOUTGo
Changed SDATOUT description in Serial Interface Operation sectionGo

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP

Top View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION	EXTERNAL COMPONENTS OR CONNECTIONS
NAME	NO.	I/O⁽¹⁾	DESCRIPTION	EXTERNAL COMPONENTS OR CONNECTIONS
POWER AND GROUND
GND	5, 12, PowerPAD™	—	Device ground	All pins must be connected to GND.
VM	1	—	Device power supply	Connect to motor supply (8.2 V - 40 V).
CONTROL
LATCH	11	I	Latch input	Rising edge latches shift register to output stage, falling edge latches fault data into output shift register – internal pulldown
nENBL	8	I	Enable input	Active low enables outputs – internal pulldown
RESET	9	I	Reset input	Active-high reset input initializes internal logic – internal pulldown
SCLK	13	I	Serial clock	Serial clock input – internal pulldown
SDATIN	14	I	Serial data input	Serial data input – internal pulldown
SDATOUT	15	OD	Serial data output	Serial data output; push-pull structure; see serial interface section for details
STATUS
nFAULT	16	OD	Fault	Logic low when in fault condition (overtemperature, overcurrent, open load) - open-drain output
OUTPUT
OUT1	3	O	Output 1	Connect to load 1
OUT2	4	O	Output 2	Connect to load 2
OUT3	6	O	Output 3	Connect to load 3
OUT4	7	O	Output 4	Connect to load 4
VCLAMP	2	—	Output clamp voltage	Connect to VM supply, or zener diode to VM supply

(1) Directions: I = input, O = output, OD = open-drain output.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
VM	Power supply voltage	–0.3	43	V
VOUTx	Output voltage	–0.3	43	V
VCLAMP	Clamp voltage	–0.3	43	V
SDATOUT, nFAULT	Output current		20	mA
	Peak clamp diode current⁽³⁾		2	A
	DC or RMS clamp diode current⁽³⁾		1	A
	Digital input pin voltage	–0.5	7	V
SDATOUT, nFAULT	Digital output pin voltage	–0.5	7	V
	Peak motor drive output current, t < 1 μS	Internally limited		A
	Continuous total power dissipation⁽³⁾	See Thermal Information
T_J	Operating virtual junction temperature⁽³⁾	–40	150	°C
T_stg	Storage temperature	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±6000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_M	Power supply voltage	8.2	40	V
V_CLAMP	Output clamp voltage⁽²⁾	0	40	V
I_OUT	Continuous output current, single channel on, T_A = 25°C⁽¹⁾		2	A
I_OUT	Continuous output current, four channels on, T_A = 25°C⁽¹⁾		1	A

(1) Power dissipation and thermal limits must be observed.

(2) VCLAMP is not a power supply input pin - it only connects to the output clamp diodes.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8806	UNIT
		PWP (HTSSOP)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	39.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.6	°C/W
R_θJB	Junction-to-board thermal resistance	20.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	20.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_A = 25°C, over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES
I_VM	VM operating supply current	V_M = 24 V		1.6	3	mA
V_UVLO	VM undervoltage lockout voltage	V_M rising			8.2	V
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
V_IL	Input low voltage				0.8	V
V_IH	Input high voltage		2			V
V_HYS	Input hysteresis			0.45		V
I_IL	Input low current	VIN = 0	–20		20	μA
I_IH	Input high current	VIN = 3.3 V			100	μA
R_PD	Pulldown resistance			100		kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
V_OL	Output low voltage	I_O = 5 mA			0.5	V
I_OH	Output high leakage current	V_O = 3.3 V			1	μA
SDATOUT OUTPUT (PUSH-PULL OUTPUT WITH INTERNAL PULLUP)
V_OL	Output low voltage	I_O = 5 mA		0.5		V
V_OH	Output high voltage	I_O = 100 µA, V_M = 11 V - 60 V, peak			6.5	V
		I_O = 100 µA, V_M = 11 V - 60 V, steady state	3.3	4.5	5.6	V
		I_O = 100 µA, V_M = 8.2 V - 11 V, steady state	2.5			V
I_SRC	Output source current	V_M= 24 V			1	mA
I_SNK	Output sink current	V_M= 24 V			5	mA
LOW-SIDE FETS
R_DS(ON)	FET on resistance	V_M = 24 V, I_O = 700 mA, T_J = 25°C		0.5		Ω
R_DS(ON)	FET on resistance	V_M = 24 V, I_O = 700 mA, T_J = 85°C		0.75	0.8	Ω
I_OFF	Open load detect current		0	25	50	μA
HIGH-SIDE DIODES
V_F	Diode forward voltage	V_M = 24 V, I_O = 700 mA, T_J = 25°C		0.9		V
I_OFF	Off state leakage current	V_M = 24 V, T_J = 25°C	–50		50	μA
OUTPUTS
t_R	Rise time	V_M = 24 V, I_O = 700 mA, Resistive load	50		300	ns
t_F	Fall time	V_M = 24 V, I_O = 700 mA, Resistive load	50		150	ns
PROTECTION CIRCUITS
I_OCP	Overcurrent protection trip level		3		5	A
t_OCP	Overcurrent protection deglitch time			3.5		µs
t_OL	Open load detect deglitch time			15		µs
t_RETRY	Overcurrent protection re-try time			1.2		ms
T_TSD	Thermal shutdown temperature	Die temperature	150	160	180	°C

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	NOM	MAX	UNIT
1	t_CYC	Clock cycle time	62			ns
2	t_CLKH	Clock high time	25			ns
3	t_CLKL	Clock low time	25			ns
4	t_SU(SDATIN)	Setup time, SDATIN to SCLK	5			ns
5	t_H(SDATIN)	Hold time, SDATIN to SCLK	1			ns
6	t_D(SDATOUT)	Delay time, SCLK to SDATOUT, no external pullup resistor, C_OUT = 100 pF		50	100	ns
7	t_W(LATCH)	Pulse width, LATCH	200			ns
8	t_OE(ENABLE)	Enable time, nENBL to output low		60		ns
9	t_D(LATCH)	Delay time, LATCH to output change		200		ns
—	t_RESET	RESET pulse width	20			µs
10	t_D(RESET)	Reset delay before clock	20			µs
11	t_STARTUP	Start-up delay VM applied before clock	55			µs

(1) Not production tested.

More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures that the last data bit is shifted into the device properly.

Figure 1. DRV8806 Timing Requirements

6.7 Typical Characteristics

Figure 2. Supply Current vs Temperature

Figure 4. R_DS(ON) vs Temperature

Figure 3. Supply Current vs Supply Voltage

Figure 5. R_DS(ON) vs Supply Voltage

7 Detailed Description

7.1 Overview

The DRV8806 is an integrated 4-channel low-side driver controlled using a serial interface to change the state of the low-side driver outputs. The low-side driver outputs consist of four N-channel MOSFETs that have a typical R_DS(ON) of 500 mΩ. A single motor supply input VM serves as device power and is internally regulated to power the low-side gate drive. Data is shifted into a temporary data register in the device through the SDATIN pin, one bit at each rising edge of SCLK, while LATCH is held low. The outputs of the device can be disabled by pulling nENBL logic high. Several safety features are integrated in the device including overcurrent protection, thermal shutdown, undervoltage lockout, and open load protection. The overcurrent protection and open load faults share a fault bit per channel that is set when one of these conditions occurs.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Output Drivers

The DRV8806 contains four protected low-side drivers. Each output has an integrated clamp diode connected to a common pin, VCLAMP.

VCLAMP can be connected to the main power supply voltage, V_M. It can also be connected to a Zener or TVS diode to V_M, allowing the switch voltage to exceed the main supply voltage V_M. This connection can be beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.

In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.

7.3.2 Protection Circuits

The DRV8806 is fully protected against undervoltage, overcurrent and overtemperature events.

7.3.2.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the t_OCP deglitch time (approximately 3.5 µs), the driver will be disabled and the nFAULT pin will be driven low. The driver will remain disabled for the t_RETRY retry time (approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either RESET pin is activated or V_M is removed and reapplied.

7.3.2.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level, operation will automatically resume.

7.3.2.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the V_M pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when V_M rises above the UVLO threshold.

7.4 Device Functional Modes

7.4.1 Serial Interface Operation

The DRV8806 is controlled with a simple serial interface. Logically, the interface is shown in Figure 6.

Figure 6. Serial Interface Operation

Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising edge of the SCLK pin, while LATCH is low. Data is shifted from the last bit to the SDATOUT pin, so multiple devices may be daisy-chained together using a single serial interface.

Note that the SDATOUT pin has a push-pull driver, which can support driving another DRV8806 SDATIN pin at clock frequencies of up to 1 MHz without an external pullup. A pullup resistor can be used between SDATOUT and an external 5-V logic supply to support higher clock frequencies. TI recommends a resistor value of approximately 1 kΩ. The SDATOUT pin is capable of approximately 1-mA source and 5-mA sink. To supply logic signals to a lower-voltage microcontroller, use a resistor divider from SDATOUT to GND.

A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage.

7.4.2 Fault Output Register

The DRV8806 contains circuitry to detect open or shorted loads. The status of the loads can be read through the serial interface. The logic is shown in Figure 7.

Figure 7. Fault Output

To overcome any leakage currents to accurately sense an open load, a small current source is connected to each output pin. This source pulls approximately 25-µA of current to ground. The voltage on the output pin is sensed during the time that the output is off, and if the voltage on the pin is less than 1.2 V (indicating that there is no load connected) after the open load deglitch time, the OPEN_FAULT latch is set. This latch is cleared whenever the output bit is set.

When the output is turned on, if an overcurrent (OCP) fault is detected, the channel will be turned off and the OCP_FAULT latch is set. This latch will be cleared whenever the output bit is cleared.

The state of the OCP_FAULT and OPEN_FAULT signals is combined into a single fault bit per channel, and loaded into a shift register while the LATCH pin is low. When the LATCH pin is taken high, the fault data is latched into the shift register at the first falling edge of SCLK. Data may then be shifted out on the SDATOUT pin on each falling edge of the SCLK pin.

Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out.

The nFAULT pin will be driven active low whenever any of the OCP_FAULT or OPEN_FAULT latches are set, as well as whenever there is an overtemperature condition.

7.4.3 Daisy-Chain Connection

Two or more DRV8806 devices may be connected together to use a single serial interface. The SDATOUT pin of the first device in the chain is connected to the SDATIN pin of the next device. The SCLK, LATCH, RESET, and nFAULT pins are connected together.

Figure 8. Daisy-Chain Connection

Figure 9 shows an example of a serial transaction, writing the output bits, and then reading the fault status bits, using two devices connected together in a daisy-chain.

Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out.

Figure 9. Daisy-Chain Serial Transaction

7.4.4 nENBL and RESET Operation

The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.

The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive RESET at power up.

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8806 can be used to drive one unipolar stepper motor.

8.2 Typical Application

Figure 10. DRV8806 Typical Application

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
Supply voltage, V_M	24 V
Motor winding resistance, R_L	7.4 Ω/phase
Motor full step angle, θ_step	1.8°/step
Motor rated current, I_RATED	0.75 A
SCLK frequency, f_SCLK	1 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Motor Voltage

The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.

8.2.2.2 Drive Current

The current path is starts from the supply V_M, moves through the inductive winding load, and low-side sinking NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.

Equation 1. P = I² × R_DS(on)

The DRV8806 has been measured to be capable of 2-A Single Channel or 1-A Four Channels in a HTSSOP package at 25°C on standard FR-4 PCBs. The maximum RMS current varies based on PCB design and the ambient temperature.

8.2.3 Application Curves

16-Ω, 1-mH, RL Load

Figure 11. Current Ramp With VM = 8.2 V

Output shorted to V_M

Figure 13. OCP With 8.2 V

16-Ω, 1-mH RL Load

Figure 12. Current Ramp With VM = 24 V

Output shorted to V_M

Figure 14. OCP With 24 V