The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DS90UH927Q-Q1 | WQFN (40) | 6.00 mm x 6.00 mm |
Changes from B Revision (June 2013) to C Revision
Changes from A Revision (November 2012) to B Revision
PIN | I/O, TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
FPD-LINK INPUT INTERFACE | |||
RxCLKIN- | 35 | I, LVDS | Inverting LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels |
RxCLKIN+ | 36 | I, LVDS | True LVDS Clock Input The pair requires external 100-Ω differential termination for standard LVDS levels |
RxIN[3:0]- | 37, 33, 31, 29 | I, LVDS | Inverting LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels |
RxIN[3:0]+ | 38, 34, 32, 30 | I, LVDS | True LVDS Data Inputs Each pair requires external 100-Ω differential termination for standard LVDS levels |
LVCMOS PARALLEL INTERFACE | |||
BKWD | 22 | I, LVCMOS w/ pull down |
Backward Compatible Mode Select BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default) BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q Requires a 10-kΩ pullup if set HIGH |
GPIO[1:0] | 40, 39 | I/O, LVCMOS w/ pull down |
General Purpose I/O See Table 1 |
I2S_DA I2S_DB I2S_DC I2S_DD |
3 4 5 6 |
I, LVCMOS w/ pull down |
Digital Audio Interface I2S Data Inputs Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3 |
I2S_WC I2S_CLK |
1 2 |
I, LVCMOS w/ pull down |
Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs Shared with GPIO_REG7 and GPIO_REG8 Table 3 |
LFMODE | 25 | I, LVCMOS w/ pull down |
Low Frequency Mode Select LFMODE = 0, 15 MHz ≤ RxCLKIN ≤ 85 MHz (Default) LFMODE = 1, 5 MHz ≤ RxCLKIN < 15 MHz Requires a 10-kΩ pullup if set HIGH |
MAPSEL | 23 | I, LVCMOS w/ pull down |
FPD-Link Input Map Select MAPSEL = 0, LSBs on RxIN3± (Default) MAPSEL = 1, MSBs on RxIN3± See Figure 19 and Figure 20 Requires a 10-kΩ pullup if set HIGH |
REPEAT | 21 | I, LVCMOS w/ pull down |
Repeater Mode Select REPEAT = 0, Repeater Mode disabled (Default) REPEAT = 1, Repeater Mode enabled Requires a 10-kΩ pullup if set HIGH |
OPTIONAL PARALLEL INTERFACE | |||
GPIO[3:2] | 6, 5 | I/O, LVCMOS w/ pull down |
General Purpose I/O Shared with I2S_DD and I2S_DC See Table 1 |
GPIO_REG[8:5] | 2, 1, 3, 4 | I/O, LVCMOS w/ pull down |
Register-Only General Purpose I/O Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB See Table 2 |
CONTROL AND CONFIGURATION | |||
IDx | 11 | I, Analog | I2C Address Select External pullup to VDD33 is required under all conditions. DO NOT FLOAT. Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider. See Figure 25 and Table 4 |
PDB | 18 | I, LVCMOS w/ pulldown |
Power-down Mode Input Pin Must be driven or pulled up to VDD33. Refer to Power Supply Recommendations. PDB = H, device is enabled (normal operation) PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET. |
SCL | 9 | I/O, LVCMOS Open Drain |
I2C Clock Input / Output Interface Must have an external pullup to VDD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
SDA | 10 | I/O, LVCMOS Open Drain |
I2C Data Input / Output Interface Must have an external pullup to VDD33. DO NOT FLOAT. Recommended pullup: 4.7 kΩ. |
STATUS | |||
INTB | 27 | O, LVCMOS Open Drain |
HDCP Interrupt INTB = H, normal INTB = L, Interrupt request Recommended pullup: 4.7 kΩ to VDDIO. DO NOT FLOAT. |
FPD-LINK III SERIAL INTERFACE | |||
CMF | 20 | Analog | Common Mode Filter. Connect 0.1 µF to GND (required) |
DOUT- | 16 | I/O, LVDS | Inverting Output The output must be AC-coupled with a 0.1-µF capacitor. |
DOUT+ | 17 | I/O, LVDS | True Output The output must be AC-coupled with a 0.1-µF capacitor. |
POWER AND GROUND(1) | |||
GND | DAP | Ground | Large metal contact at the bottom center of the device package Connect to the ground plane (GND) with at least 9 vias. |
VDD33_A VDD33_B |
19 26 |
Power | Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7 µF capacitor to GND |
VDDIO | 7, 24 | Power | LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7 µF capacitor to GND |
REGULATOR CAPACITOR | |||
CAPP12 CAPHS12 CAPLVD12 |
12 14 28 |
CAP | Decoupling capacitor connection for on-chip regulator Each requires a 4.7-µF decoupling capacitor to GND. |
CAPL12 | 8 | CAP | Decoupling capacitor connection for on-chip regulator Requires two 4.7-µF decoupling capacitors to GND |
OTHER | |||
RES[1:0] | 15, 13 | GND | Reserved Connect to GND. |
MIN | MAX | UNIT | |
---|---|---|---|
Supply Voltage – VDD33(4) | −0.3 | 4.0 | V |
Supply Voltage – VDDIO(4) | −0.3 | 4.0 | V |
LVCMOS I/O Voltage | −0.3 | (VDDIO + 0.3) | V |
Serializer Output Voltage | −0.3 | 2.75 | V |
Junction Temperature | 150 | °C | |
Storage Temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||||
---|---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±8000 | V | ||
Charged device model (CDM), per AEC Q100-011 | ±1250 | |||||
Machine model (MM) | ±250 | |||||
(IEC 61000-4-2, powered-up only) RD = 330 Ω, CS = 150 pF |
Air Discharge (Pin 16 and 17) |
±15000 | V | |||
Contact Discharge (Pin 16 and 17) |
±8000 | |||||
(ISO 10605) RD = 330 Ω, CS = 150 pF/330 pF RD = 2 kΩ, CS = 150 pF/330 pF |
Air Discharge (Pin 16 and 17) |
±15000 | ||||
Contact Discharge (Pin 16 and 17) |
±8000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply Voltage (VDD33) | 3 | 3.3 | 3.6 | V | |
LVCMOS Supply Voltage (VDDIO)(2) | Connect VDDIO to 3.3 V and use 3.3-V IOs | 3 | 3.3 | 3.6 | V |
Connect VDDIO to 1.8 V and use 1.8-V IOs | 1.71 | 1.8 | 1.89 | V | |
Operating Free Air Temperature (TA) | −40 | +25 | +105 | °C | |
PCLK Frequency | 5 | 85 | MHz | ||
Supply Noise(1) | 100 | mVP-P |
THERMAL METRIC(1) | DS90UH927Q-Q1 | UNIT | |
---|---|---|---|
RTA (WQFN) | |||
40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 29.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.4 | |
RθJB | Junction-to-board thermal resistance | 5.1 | |
ψJT | Junction-to-top characterization parameter | 0.2 | |
ψJB | Junction-to-board characterization parameter | 5.1 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.4 |
PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
LVCMOS I/O | ||||||||
VIH | High Level Input Voltage | VDDIO = 3.0 V to 3.6 V(4) | PDB | 2.0 | VDDIO | V | ||
VIL | Low Level Input Voltage | VDDIO = 3.0 V to 3.6 V(4) | GND | 0.8 | V | |||
IIN | Input Current | VIN = 0 V or VDDIO = 3.0 V to 3.6 V(4) | −15 | ±1 | +15 | μA | ||
VIH | High Level Input Voltage | VDDIO = 3.0 V to 3.6 V | GPIO[1:0] I2S_CLK I2S_WC I2S_D [A,B,C,D] LFMODE MAPSEL BKWD REPEAT |
2.0 | VDDIO | V | ||
VDDIO = 1.71 V to 1.89 V | 0.65× VDDIO |
VDDIO | V | |||||
VIL | Low Level Input Voltage | VDDIO = 3.0 V to 3.6 V | GND | 0.8 | V | |||
VDDIO = 1.71 V to 1.89 V | GND | 0.35* VDDIO |
V | |||||
IIN | Input Current | VIN = 0 V or VDDIO | VDDIO = 3.0 V to 3.6 V | −15 | ±1 | +15 | μA | |
VDDIO = 1.71 V to 1.89 V | −15 | ±1 | +15 | μA | ||||
VOH | High Level Output Voltage | IOH = −4 mA | VDDIO = 3.0 V to 3.6 V | GPIO[3:0], GPO_REG [8:5] |
2.4 | VDDIO | V | |
VDDIO = 1.71 V to 1.89 V | VDDIO - 0.45 | VDDIO | V | |||||
VOL | Low Level Output Voltage | IOL = +4 mA | VDDIO = 3.0 V to 3.6 V | GND | 0.4 | V | ||
VDDIO = 1.71 V to 1.89 V | GND | 0.45 | V | |||||
IOS | Output Short Circuit Current(5) | VOUT = 0 V | −55 | mA | ||||
IOZ | TRI-STATE® Output Current | VOUT = 0 V or VDDIO, PDB = L, | −15 | +15 | μA | |||
FPD-LINK LVDS RECEIVER | ||||||||
VTH | Threshold High Voltage | VCM = 1.2 V | RxCLKIN± RxIN[3:0]± |
+100 | mV | |||
VTL | Threshold Low Voltage | −100 | mV | |||||
|VID| | Differential Input Voltage Swing | 200 | 600 | mV | ||||
VCM | Common Mode Voltage | 0 | 1.2 | 2.4 | V | |||
IIN | Input Current | −10 | +10 | μA | ||||
FPD-LINK III CML DRIVER | ||||||||
VODp-p | Differential Output Voltage (DOUT+) – (DOUT-) |
RL = 100 Ω | DOUT± | 800 | 1000 | 1200 | mVp-p | |
ΔVOD | Output Voltage Unbalance | 1 | 50 | mV | ||||
VOS | Offset Voltage – Single-ended | RL = 100 Ω | 2.5-0.25* VODp-p (TYP) |
V | ||||
ΔVOS | Offset Voltage Unbalance Single-ended |
1 | 50 | mV | ||||
IOS | Output Short Circuit Current | DOUT+/- = 0V, PDB = L or H | mA | |||||
RT | Internal Termination Resistance - Differential | 80 | 100 | 120 | Ω | |||
SUPPLY CURRENT | ||||||||
IDD1 | Supply Current RL = 100Ω, PCLK = 85MHz |
Checkerboard Pattern | VDD33= 3.6 V | 135 | 160 | mA | ||
IDDIO1 | VDDIO = 3.6 V | 100 | 500 | μA | ||||
VDDIO = 1.89 V | 200 | 600 | μA | |||||
IDD2 | Random Pattern PRBS7 |
VDD33= 3.6 V | 133 | mA | ||||
IDDIO2 | VDDIO = 3.6 V | 100 | μA | |||||
VDDIO = 1.89 V | 100 | μA | ||||||
IDDS | Supply Current — Remote Auto Power Down | reg_0x01[7]=1, Back channel Idle | VDD33 = 3.6 V | 1.2 | 2.4 | mA | ||
IDDIOS | VDDIO = 3.6 V | 4 | 30 | μA | ||||
VDDIO = 1.89 V | 5 | 30 | μA | |||||
IDDZ | Supply Current — Power Down | PDB = 0 V, All other LVCMOS inputs = 0 V | VDD33 = 3.6 V | 1 | 2.2 | mA | ||
IDDIOZ | VDDIO = 3.6 V | 8 | 20 | μA | ||||
VDDIO = 1.89 V | 4 | 20 | μA |
PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
FPD-LINK LVDS INPUT | |||||||
tRSP | Receiver Strobe Position | See Figure 4 | RxCLKIN±, RXIN[3:0]± | 0.25 | 0.5 | 0.75 | UI |
FPD-LINK III CML I/O | |||||||
tLHT | CML Output Low-to-High Transition Time | See Figure 3 | DOUT+, DOUT- | 100 | 140 | ps | |
tHLT | CML Output High-to-Low Transition Time | 100 | 140 | ps | |||
tPLD | Serializer PLL Lock Time | See Figure 5, (4) | PCLK = 5 MHz to 85 MHz | 5 | ms | ||
tSD | Delay — Latency | See Figure 6 | 146*T | ns | |||
tTJIT | Output Total Jitter, Bit Error Rate ≤1E-9, see Figure 7, (5)(6)(7)(8)(9) |
Checkerboard Pattern PCLK=5 MHz, see Figure 8 |
RxCLKIN± | 0.17 | 0.2 | UI | |
Checkerboard Pattern PCLK=85 MHz, see Figure 8 |
0.26 | 0.29 | UI | ||||
tIJIT | Input Jitter Tolerance, Bit Error Rate ≤1E-9 (8)(10) | f/40 < Jitter Freq < f/20, DES = DS90UH926Q-Q1 | RxCLKIN±, f = 78 MHz | 0.6 | UI | ||
f/40 < Jitter Freq < f/20, DES = DS90UH928Q-Q1 | 0.5 | UI | |||||
I2S RECEIVER | |||||||
TI2S | I2S Clock Period, see Figure 10, (7)(11) | RxCLKIN± f=5 MHz to 85 MHz | I2S_CLK, PCLK = 5 MHz to 85 MHz | >4 / PCLK or >77 | ns | ||
THC | I2S Clock High Time, see Figure 10, (11) | I2S_CLK | 0.35 | TI2S | |||
TLC | I2S Clock Low Time, see Figure 10, (11) | I2S_CLK | 0.35 | TI2S | |||
tsr | I2S Set-up Time | I2S_WC I2S_D[A,B,C,D] |
0.2 | TI2S | |||
thtr | I2S Hold Time | I2S_WC I2S_D[A,B,C,D] |
0.2 | TI2S | |||
OTHER I/O | |||||||
tGPIO,FC | GPIO Pulse Width, Forward Channel | GPIO[3:0], PCLK = 5 MHz to 85 MHz | >2/PCLK | s | |||
tGPIO,BC | GPIO Pulse Width, Back Channel | GPIO[3:0] | 20 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | Input High Level | SDA and SCL | 0.7* VDDIO |
VDD33 | V | |
VIL | Input Low Level Voltage | SDA and SCL | GND | 0.3* VDD33 |
V | |
VHY | Input Hysteresis | >50 | mV | |||
VOL | SDA or SCL, IOL = 1.25 mA | 0 | 0.36 | V | ||
Iin | SDA or SCL, Vin = VDDIO or GND | -10 | +10 | µA | ||
Cin | Input Capacitance | SDA or SCL | <5 | pF |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSCL | SCL Clock Frequency | Standard Mode | 0 | 100 | kHz | |
Fast Mode | 0 | 400 | kHz | |||
tLOW | SCL Low Period | Standard Mode | 4.7 | µs | ||
Fast Mode | 1.3 | µs | ||||
tHIGH | SCL High Period | Standard Mode | 4.0 | µs | ||
Fast Mode | 0.6 | µs | ||||
tHD;STA | Hold time for a start or a repeated start condition, see Figure 9
|
Standard Mode | 4.0 | µs | ||
Fast Mode | 0.6 | µs | ||||
tSU:STA | Set Up time for a start or a repeated start condition, see Figure 9 | Standard Mode | 4.7 | µs | ||
Fast Mode | 0.6 | µs | ||||
tHD;DAT | Data Hold Time, see Figure 9 | Standard Mode | 0 | 3.45 | µs | |
Fast Mode | 0 | 0.9 | µs | |||
tSU;DAT | Data Set Up Time, see Figure 9 | Standard Mode | 250 | ns | ||
Fast Mode | 100 | ns | ||||
tSU;STO | Set Up Time for STOP Condition, see Figure 9 | Standard Mode | 4.0 | µs | ||
Fast Mode | 0.6 | µs | ||||
tBUF | Bus Free Time Between STOP and START, see Figure 9 |
Standard Mode | 4.7 | µs | ||
Fast Mode | 1.3 | µs | ||||
tr | SCL & SDA Rise Time, see Figure 9 | Standard Mode | 1000 | ns | ||
Fast Mode | 300 | ns | ||||
tf | SCL & SDA Fall Time, see Figure 9 | Standard Mode | 300 | ns | ||
Fast mode | 300 | ns |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tR | SDA RiseTime – READ | SDA, RPU = 10 kΩ, Cb ≤ 400 pF, see Figure 9 | 430 | ns | ||
tF | SDA Fall Time – READ | 20 | ns | |||
tSU;DAT | Set Up Time — READ | See Figure 9 | 560 | ns | ||
tHD;DAT | Hold Up Time — READ | See Figure 9 | 615 | ns | ||
tSP | Input Filter | 50 | ns |