SNOS521E
January 2001 – January 2018
DS92LV040A
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Functional Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
7
Parameter Measurement Information
7.1
Test Circuits and Timing Waveforms
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Multipoint Communications
9.2.2
Design Requirements
9.2.3
Detailed Design Procedure
9.2.3.1
Supply Voltage
9.2.3.2
Supply Bypass Capacitance
9.2.3.3
Termination Resistors
9.2.3.4
Interconnecting Media
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Microstrip vs. Stripline Topologies
11.1.2
Dielectric Type and Board Construction
11.1.3
Recommended Stack Layout
11.1.4
Separation Between Traces
11.1.5
Crosstalk and Ground Bounce Minimization
11.1.6
Decoupling
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
NJN|44
MPQS017
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snos521e_oa
snos521e_pm
1
Features
Bus LVDS Signaling
Propagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns Max
Low power CMOS Design
100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver Typical
High Signaling Rate Capability (above 155 Mbps)
0.1 V to 2.3 V Common Mode Range for
V
ID
= 200 mV
70 mV Receiver Sensitivity
Supports Open and Terminated Failsafe on Port Pins
3.3-V Operation
Glitch Free Power up/down (Driver & Receiver Disabled)
Light Bus Loading (5 pF Typical) per Bus LVDS Load
Balanced Output Impedance
Product Offered in 44 Pin WQFN Package
High Impedance Bus Pins on Power Off
(V
CC
= 0 V)