HD3SS6126 USB 3.0 and USB 2.0 Differential Switch 2:1/1:2 MUX/DEMUX
- SLAS975A November 2013 – August 2015 HD3SS6126
  
  PRODUCTION DATA.

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DATA SHEET

HD3SS6126 USB 3.0 and USB 2.0 Differential Switch 2:1/1:2 MUX/DEMUX

1 Features

Ideal for USB Applications
- Signal Switch for USB 3.0 (SuperSpeed USB and USB 2.0 HS/FS/LS)
Three Bidirectional Differential Pair Channel MUX/DEMUX Switches Also Suitable for DisplayPort, PCIe Gen1/2/3, SATA 1.5/3/6G, SAS 1.5/3/6G and XAUI Applications
Supports Data Rates up to 10 Gbps on High-Bandwidth Path (SS)
V_CC Operating Range 3.3 V ± 10%
Wide –3-dB Differential BW of More Than 10 GHz on High-Bandwidth Path (SS)
Uses a Unique Adaptation Method to Maintain a Constant Channel Impedance Over the Supported Common-Mode Voltage Range
Excellent High-bandwidth Path Dynamic Characteristics (at 2.5 GHz)
- Crosstalk = –35 dB
- Isolation = –23 dB
- Insertion Loss = –1.1 dB
- Return Loss = –11 dB
Small 3.5 mm × 9 mm, 42-Pin WQFN Package (RUA)
Active Mode Power = 8 mW

2 Applications

Desktop PCs
Notebook PCs
Tablets
Docking Stations
Telecommunications
Televisions

3 Description

The HD3SS6126 device is a high-speed, passive switch that is designed for USB applications to route both SuperSpeed USB RX and TX and USB 2.0 DP and DM signals from a source to two destinations or vice versa. The device can also be used for DisplayPort, PCI-Express™, SATA, SAS, and XAUI applications. The HD3SS6126 device can be used in either sink-side or source-side applications.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
HD3SS6126	WQFN (42)	9.00 mm × 3.50 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

4 Revision History

Changes from * Revision (November 2013) to A Revision

Added Pin Configuration and Functions section, ESD Ratings table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

RUA Package

42-Pin WQFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
GND	10, 14, 17, 19, 21	Supply	Ground
HSA(p)	8	I/O	Port A USB 2.0 positive signal
HSA(n)	7	I/O	Port A USB 2.0 negative signal
HSB(p)	31	I/O	Port B USB 2.0 positive signal
HSB(n)	32	I/O	Port B USB 2.0 negative signal
HSC(p)	33	I/O	Port C USB 2.0 positive signal
HSC(n)	34	I/O	Port C USB 2.0 negative signal
HS_OE	6	I (Control)	Output Enable H = Power Down L = Normal Operation
NC	1, 2, 3, 4, 5, 18, 35, 36, 37, 38, 39, 40, 41, 42	—	Electrically No Connection
SEL	9	I (Control)	USB 3.0/2.0 Port Selection Control Pins
SSA0(p)	11	I/O	Port A, Channel 0, USB 3.0 Positive Signal
SSA0(n)	12	I/O	Port A, Channel 0, USB 3.0 Negative Signal
SSA1(p)	15	I/O	Port A, Channel 1, USB 3.0 Positive Signal
SSA1(n)	16	I/O	Port A, Channel 1, USB 3.0 Negative Signal
SSB0(p)	29	I/O	Port B, Channel 0, USB 3.0 Positive Signal
SSB0(n)	28	I/O	Port B, Channel 0, USB 3.0 Negative Signal
SSB1(p)	27	I/O	Port B, Channel 1, USB 3.0 Positive Signal
SSB1(n)	26	I/O	Port B, Channel 1, USB 3.0 Negative Signal
SSC0(p)	25	I/O	Port C, Channel 0, USB 3.0 Positive Signal
SSC0(n)	24	I/O	Port C, Channel 0, USB 3.0 Negative Signal
SSC1(p)	23	I/O	Port C, Channel 1, USB 3.0 Positive Signal
SSC1(n)	22	I/O	Port C, Channel 1, USB 3.0 Negative Signal
VDD	13, 20, 30	Supply	3.3-V power supply voltage

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply Voltage, V_DD⁽²⁾		–0.3	4	V
Voltage	Differential I/O, High-bandwidth signal path: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)	–0.5	4	V
	Differential I/O, Low-bandwidth signal path: HSAp/n), HSB(p/n), HSC(p/n)	-0.5	7
	Control pin and single ended I/O	–0.3	V_DD + 0.3
Continuous power dissipation		See Thermal Information
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

typical values for all parameters are at V_CC = 3.3 V and T_A = 25°C; all temperature limits are specified by design

			MIN	NOM	MAX	UNIT
V_DD	Supply voltage		3.0	3.3	3.6	V
V_IH	Input high voltage	Control Pins	2.0		V_DD	V
V_IL	Input low voltage	Control Pins	–0.1		0.8	V
V_{I/O_Diff}	Differential voltage	Switch I/O differential voltage for High-bandwidth signal path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)	0		1.8	V_p-p
V_{I/O_CM}	Common voltage	Switch I/O common mode voltage for High-bandwidth signal path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)	0		2.0	V
T_A	Operating free-air temperature		0		70	°C

6.4 Thermal Information

THERMAL METRIC		HD3SS6126	UNIT
		RUA (WQFN)
		42 PINS
R_θJA	Junction-to-ambient thermal resistance	53.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	38.2	°C/W
R_θJB	Junction-to-board thermal resistance	27.4	°C/W
ψ_JT	Junction-to-top characterization parameter ⁽¹⁾	5.6	°C/W
ψ_JB	Junction-to-board characterization parameter ⁽¹⁾	27.3	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report, SPRA953. Test conditions for Ψ_JB and Ψ_JT are clarified in the application report..

6.5 Electrical Characteristics – Device Parameters

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
I_CC	Supply current	V_DD = 3.6 V, SEL = V_DD /GND; OE = GND; Outputs Floating	2.4	3	mA
SEL
I_IH	Input high current	V_DD = 3.6 V, V_IN = V_DD		95	µA
I_IL	Input high current	V_DD = 3.6 V, V_IN = GND		1	µA
HS_OE
I_IH	Input high current	V_DD = 3.6 V, V_IN = V_DD		1	µA
I_IL	Input high current	V_DD = 3.6 V, V_IN = GND		1	µA
SSA0/1, SSB0/1, SSC0/1
I_LK	High-impedance leakage current	V_DD = 3.6 V, V_IN = 2 V, V_OUT= 2 V, (I_LK on open outputs Port B and C)		130	µA
I_LK	High-impedance leakage current	V_DD = 3.6 V, V_IN = 2 V, V_OUT= 2 V, (I_LK on open outputs Port A)		4	µA
HSA, HSB, HSC
I_LK	High-impedance leakage current	V_DD = 3.6 V, V_IN = 0 V, V_OUT= 0 V to 4 V, HS_OE_IN = GND		1	µA

6.6 Electrical Characteristics – Signal Switch Parameters

under recommended operating conditions; R_L, R_SC= 50 Ω, C_L = 10 pF (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
C_ON	Outputs ON capacitance	V_IN = 0 V, outputs open, switch ON	1.5		pF
C_OFF	Outputs OFF capacitance	V_IN = 0 V, outputs open, switch OFF	1		pF
R_ON	Output ON resistance	V_DD = 3.3 V, V_CM = 0 V – 2 V, I_O = –8 mA	5	8	Ω
ΔR_ON	ON resistance match between pairs of the same channel	V_DD = 3.3 V; 0 V ≤ V_IN ≤ 2 V; I_O = –8 mA		0.7	Ω
R_{FLAT_ON}	ON resistance flatness (R_ON(MAX)– R_ON(MIN)	V_DD = 3.3 V; –0 V ≤ V_IN ≤ 2 V		1.15	Ω
R_L	Differential return loss (V_CM = 0 V)	f = 0.3 MHz	–25		dB
		f = 2.5 GHz	–11
		f = 4 GHz	–11
X_TALK	Differential crosstalk (V_CM = 0 V)	f = 0.3 MHz	-85		dB
		f = 2.5 GHz	–35
		f = 4 GHz	–33
O_IRR	Differential off-isolation (V_CM = 0 V)	f = 0.3 MHz	-85		dB
		f = 2.5 GHz	-23
		f = 4 GHz	–21
I_L	Differential insertion loss (V_CM = 0 V)	f = 0.3 MHz	–0.43		dB
		f = 2.5 GHz	–1.1
		f = 4 GHz	–1.3
BW	Bandwidth	At –3 dB	10		GHz
HSA(p/n), HSB(p/n), HSC(p/n) SIGNAL PATH
C_ON	Outputs ON capacitance	V_IN = 0 V, Outputs Open, Switch ON	6	7.5	pF
C_OFF	Outputs OFF capacitance	V_IN = 0 V, Outputs Open, Switch OFF	3.5	6	pF
R_ON	Output ON resistance	V_DD = 3 V, V_IN = 0 V, I_O = 30 mA	3	6	Ω
R_ON	Output ON resistance	V_DD = 3 V, V_IN = 2.4 V, I_O = 30 mA	3.4	6	Ω
ΔR_ON	ON resistance match between pairs of the same channel	V_DD = 3 V; V_IN = 0 V; I_O = 30 mA	0.2		Ω
ΔR_ON	ON resistance match between pairs of the same channel	V_DD = 3 V; V_IN = 1.7 V; I_O = -15 mA	0.2		Ω
R_{FLAT_ON}	ON resistance flatness (R_ON(MAX)– R_{ON(MIN )}	V_DD = 3 V; V_IN = 0 V; I_O = 30 mA	1		Ω
R_{FLAT_ON}	ON resistance flatness (R_ON(MAX)– R_{ON(MIN )}	V_DD = 3 V; V_IN = 1.7 V; I_O = –15 mA	1		Ω
X_TALK	Differential crosstalk (V_CM = 0 V)	R_L = 50 Ω, f = 250 MHz	–40		dB
O_IRR	Differential off-isolation (V_CM = 0 V)	R_L = 50 Ω, f = 250 MHz	–41		dB
BW	Bandwidth	R_L = 50 Ω	0.9		GHz

(1) Specified by design

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
t_on	SEL-to-Switch t_on	R_SC and R_L = 50 Ω, See Figure 1	70	250	ns
t_off	SEL-to-Switch t_off	R_SC and R_L = 50 Ω, See Figure 1	70	250	ns
t_PD	Switch propagation delay	R_SC and R_L = 50 Ω, See Figure 3		85	ps
t_SK(O)	Interpair output skew (CH-CH)	R_SC and R_L = 50 Ω, See Figure 3		20	ps
t_SK(b-b)	Intrapair Output Skew (bit-bit)	R_SC and R_L = 50 Ω, See Figure 3		8	ps
HSA(p/n), HSB(p/n), HSC(p/n) SIGNAL PATH
t_ON	SEL to Switch t_ON	See Figure 2		30	ns
t_ON	HS_OE to Switch t_ON	See Figure 2		17	ns
t_OFF	SEL to Switch t_OFF	See Figure 2		12	ns
t_OFF	HS_OE to Switch t_OFF	See Figure 2		10	ns
t_PD⁽¹⁾	Switch propagation delay	See Figure 3	250		ps
t_SK(O)⁽¹⁾	Interpair output skew (CH-CH)		100	200	ps
t_SK(P)⁽¹⁾	Intrapair Output Skew (bit-bit)		100	200	ps

Figure 1. Select to Switch t_ON and t_OFF

Figure 2. Turnon (t_ON) and Turnoff Time (t_OFF)

Figure 3. Propagation Delay and Skew

6.8 Typical Characteristics

Figure 4. Intrapair Skew SSA to SSB Port

Figure 5. Intrapair Skew SSA to SSC Port