ISO5852S-Q1 High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features

1 Features

• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
  • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
  • Device HBM Classification Level 3A
  • Device CDM Classification Level C6
• 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at V_CM = 1500 V
• Split Outputs to Provide 2.5-A Peak Source and
  5-A Peak Sink Currents
• Short Propagation Delay: 76 ns (Typ),
  110 ns (Max)
• 2-A Active Miller Clamp
• Output Short-Circuit Clamp
• Soft Turn-Off (STO) during Short Circuit
• Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
• Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
• Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
• 2.25-V to 5.5-V Input Supply Voltage
• 15-V to 30-V Output Driver Supply Voltage
• CMOS Compatible Inputs
• Rejects Input Pulses and Noise Transients Shorter Than 20 ns
• Isolation Surge Withstand Voltage 12800-V_PK
• Safety-Related Certifications:
  • 8000-V_PK V_IOTM and 2121-V_PK V_IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
  • 5700-V_RMS Isolation for 1 Minute per UL 1577
  • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
  • TUV Certification per EN 61010-1 and EN 60950-1
  • GB4943.1-2011 CQC Certification
  • All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA

2 Applications

• Isolated IGBT and MOSFET Drives in:
  • HEV and EV Power Modules
  • Industrial Motor Control Drives
  • Industrial Power Supplies
  • Solar Inverters
  • Induction Heating

3 Description

The ISO5852S-Q1 device is a 5.7-kV_RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V_EE2, the gate-driver output is pulled hard to the V_EE2 potential, turning the IGBT immediately off.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

4 Revision History

Changes from * Revision (September 2016) to A Revision

• Changed the title of the data sheet from Active Safety Features to Active Protection FeaturesGo
• Changed the Electrostatic Discharge CautionGo

5 Description (continued)

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V_EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

6 Pin Configuration and Function

7 Specifications

The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.11 Insulation Characteristics Curves

TA up to 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Reinforced Isolation Capacitor Lifetime Projection

1.

Figure 3. Thermal Derating Curve for Limiting Power per VDE

Figure 2. Thermal Derating Curve for Limiting Current per VDE

7.12 Typical Characteristics

Figure 4. Output High Drive Current vs Temperature

Figure 6. Output Low Drive Current vs Temperature

Unipolar: VCC2 – VEE2 = VCC2 – GND2

Figure 8. DESAT Threshold Voltage vs Temperature

Figure 5. Output High Drive Current vs Output Voltage

Figure 7. Output Low Drive Current vs Output Voltage

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 9. Output Transient Waveform

CL = 100 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 11. Output Transient Waveform

CL = 10 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 13. Output Transient Waveform

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V		DESAT = 220 pF

Figure 15. Output Transient Waveform DESAT, RDY, and FLT

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 30 V		DESAT = 220 pF

Figure 17. Output Transient Waveform DESAT, RDY, and FLT

IN+ = High

IN– = Low

Figure 19. I_CC1 Supply Current vs Temperature

Figure 21. I_CC1 Supply Current vs Input Frequency

No CL

Figure 23. I_CC2 Supply Current vs Input Frequency

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC1 = 5 V

Figure 25. Propagation Delay vs Temperature

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 27. Propagation Delay vs Load Capacitance

RGH = 0 Ω

RGL = 0 Ω

VCC1 = 5 V

Figure 29. t_f Fall Time v. Load Capacitance

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 31. t_f Fall Time vs Load Capacitance

CL = 10 nF

RGH = 0 Ω

RGL = 0 Ω

Figure 33. DESAT Sense to V_OUT 10% Delay vs Temperature

Figure 35. DESAT Sense to Fault Low Delay vs Temperature

Figure 37. Reset to Fault Delay Across Temperature

Figure 39. Active Pulldown Voltage vs Temperature

Figure 41. V_{OUTH_CLAMP} - Short-Circuit Clamp Voltage on OUTH Across Temperature

VCC2 = 15 V

DESAT = 6 V

Figure 43. Blanking Capacitor Charging Current vs Temperature

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 10. Output Transient Waveform

CL = 1 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 12. Output Transient Waveform

CL = 100 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 14. Output Transient Waveform

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V		DESAT = 220 pF

Figure 16. Output Transient Waveform DESAT, RDY, and FLT

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 30 V		DESAT = 220 pF

Figure 18. Output Transient Waveform DESAT, RDY, and FLT

IN+ = Low

IN– = Low

Figure 20. I_CC1 Supply Current vs Temperature

Input frequency = 1 kHz

Figure 22. I_CC2 Supply Current vs Temperature

RGH = 10 Ω

RGL = 5 Ω, 20 kHz

Figure 24. I_CC2 Supply Current vs Load Capacitance

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 = 15 V

Figure 26. Propagation Delay vs Temperature

RGH = 0 Ω

RGL = 0 Ω

VCC1 = 5 V

Figure 28. t_r Rise Time vs Load Capacitance

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 30. t_r Rise Time vs Load Capacitance

Figure 32. Leading Edge Blanking Time With Temperature

CL = 10 nF

RGH = 0 Ω

RGL = 0 Ω

Figure 34. DESAT Sense to V_OUT 90% Delay vs Temperature

Figure 36. Fault and RDY Low to RDY High Delay vs Temperature

Figure 38. Miller Clamp Current vs Temperature

Figure 40. V_{CLP_CLAMP} - Short-Circuit Clamp Voltage on Clamp Across Temperature

Figure 42. V_{OUTL_CLAMP} - Short-Circuit Clamp Voltage on OUTL Across Temperature

8 Parameter Measurement Information

Figure 44. OUTH and OUTL Propagation Delay, Non-Inverting Configuration

Figure 45. OUTH and OUTL Propagation Delay, Inverting Configuration

Figure 46. DESAT, OUTH/L, FLT, RST Delay

Figure 47. Common-Mode Transient Immunity Test Circuit