ISO7640FM and ISO7641FM provide galvanic isolation up to 6 KVPK for 1 minute per UL and VDE. These devices are also certified up to 5-KVRMS Reinforced isolation at a working voltage of 400 VRMS per end equipment standards EN/UL/CSA 60950-1 and 61010-1. ISO7640F and ISO7641F are quad-channel isolators; ISO7640F has four forward and ISO7641F has three forward and one reverse-direction channels. Suffix F indicates that output defaults to Low-state in fail-safe conditions (see Table 4). M-Grade devices are high-speed isolators capable of 150-Mbps data rate with fast propagation delays.
Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and can operate from 2.7-V, 3.3-V, and 5-V supplies. All inputs are 5-V tolerant when supplied from 3.3-V or 2.7-V supplies.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7640FM | SOIC (16) | 10.30 mm × 7.50 mm |
ISO7641FM |
Changes from F Revision (September 2013) to G Revision
Changes from E Revision (January 2013) to F Revision
Changes from D Revision (July 2012) to E Revision
Changes from C Revision (January 2012) to D Revision
Changes from B Revision (December 2011) to C Revision
Changes from A Revision (October 2011) to B Revision
Changes from * Revision (September 2011) to A Revision
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Supply voltage(2) | VCC1, VCC2 | –0.5 | 6 | V | ||
Voltage | INx, OUTx, ENx | –0.5 | VCC + 0.5(3) | V | ||
Output Current, IO | –15 | 15 | mA | |||
Maximum junction temperature, TJ | 150 | °C | ||||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±4000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1500 | |||
Machine model, per JEDEC JESD22-A115-A | ±200 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 2.7 | 5.5 | V | |||
IOH | High-level output current | –4 | mA | ||||
IOL | Low-level output current | 4 | mA | ||||
VIH | High-level input voltage | 2 | 5.5 | V | |||
VIL | Low-level input voltage | 0 | 0.8 | V | |||
tui | Input pulse duration | ≥3-V Operation | 6.67 | ns | |||
<3-V Operation | 10 | ||||||
1 / tui | Signaling rate | ≥3-V Operation | 0 | 150 | Mbps | ||
<3-V Operation | 0 | 100 | |||||
TJ | Junction temperature | –40 | 136 | °C | |||
TA | Ambient temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO76xx | UNIT | ||
---|---|---|---|---|
DW (SOIC) | ||||
16 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 72 | °C/W | |
RθJC(top) | Junction-to-case(top) thermal resistance | 38 | ||
RθJB | Junction-to-board thermal resistance | 39 | ||
ψJT | Junction-to-top characterization parameter | 9.4 | ||
PD | Maximum Device Power Dissipation | VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15 pF Input a 75-MHz 50% duty cycle square wave |
399 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 9 | VCCO(1) –0.8 | 4.8 | V | ||
IOH = –20 μA; see Figure 9 | VCCO(1) –0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 9 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 9 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 450 | mV | ||||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 12 | 25 | 75 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 9 | OUTx on VCC1 (5V) side | VCC1 – 0.8 | 4.8 | V | |
OUTx on VCC2 (3.3V) side | VCC2 – 0.4 | 3 | |||||
IOH = –20 μA; see Figure 9 | OUTx on VCC1 (5V) side | VCC1 – 0.1 | 5 | ||||
OUTx on VCC2 (3.3V) side | VCC2 – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 9 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 9 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 430 | mV | ||||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 12 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 9 | OUTx on VCC1 (3.3 V) side | VCC1–0.4 | 3 | V | |
OUTx on VCC2 (5 V) side | VCC2–0.8 | 4.8 | |||||
IOH = –20 μA; see Figure 9 | OUTx on VCC1 (3.3 V) side | VCC1–0.1 | 3.3 | ||||
OUTx on VCC2 (5 V) side | VCC2–0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 9 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 9 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 430 | mV | ||||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 12 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 9 | VCCO(1) – 0.4 | 3 | V | ||
IOH = –20 μA; see Figure 9 | VCCO(1) – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 9 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 9 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 12 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 9 | VCCO(2) – 0.5 | 2.4 | V | ||
IOH = –20 μA; see Figure 9 | VCCO(2) – 0.1 | 2.7 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 9 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 9 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 350 | mV | ||||
IIH | High-level input current | VIH = VCC at INx or ENx | 10 | μA | |||
IIL | Low-level input current | VIL = 0 V at INx or ENx | –10 | ||||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 12 | 25 | 50 | kV/μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISO7640FM | |||||||
ICC1 | Disable | EN = 0 V | 0.6 | 1.2 | mA | ||
ICC2 | 4.5 | 6.6 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
0.7 | 1.3 | |||
ICC2 | 4.6 | 6.7 | |||||
ICC1 | 10 Mbps | 1.1 | 2 | ||||
ICC2 | 6.6 | 10.5 | |||||
ICC1 | 25 Mbps | 1.9 | 3 | ||||
ICC2 | 9.7 | 14.7 | |||||
ICC1 | 150 Mbps | 8.2 | 14.5 | ||||
ICC2 | 35 | 58 | |||||
ISO7641FM | |||||||
ICC1 | Disable | EN1 = EN2 = 0 V | 2.6 | 4.2 | mA | ||
ICC2 | 4.2 | 6.8 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
2.7 | 4.3 | |||
ICC2 | 4.3 | 6.9 | |||||
ICC1 | 10 Mbps | 3.6 | 4.9 | ||||
ICC2 | 6 | 8.2 | |||||
ICC1 | 25 Mbps | 5.1 | 6.6 | ||||
ICC2 | 8.8 | 11.4 | |||||
ICC1 | 150 Mbps | 17 | 22 | ||||
ICC2 | 31 | 42 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISO7640FM | |||||||
ICC1 | Disable | EN = 0 V | 0.6 | 1.2 | mA | ||
ICC2 | 3.6 | 5.1 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
0.7 | 1.3 | |||
ICC2 | 3.7 | 5.2 | |||||
ICC1 | 10 Mbps | 1.1 | 2 | ||||
ICC2 | 5 | 7.1 | |||||
ICC1 | 25 Mbps | 1.9 | 3 | ||||
ICC2 | 6.9 | 11 | |||||
ICC1 | 150 Mbps | 8.2 | 14.5 | ||||
ICC2 | 24 | 40 | |||||
ISO7641FM | |||||||
ICC1 | Disable | EN1 = EN2 = 0 V | 2.6 | 4.2 | mA | ||
ICC2 | 3.2 | 4.9 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
2.7 | 4.3 | |||
ICC2 | 3.3 | 5 | |||||
ICC1 | 10 Mbps | 3.6 | 4.9 | ||||
ICC2 | 4.4 | 5.8 | |||||
ICC1 | 25 Mbps | 5.1 | 6.6 | ||||
ICC2 | 6.1 | 7.6 | |||||
ICC1 | 150 Mbps | 17 | 22 | ||||
ICC2 | 20.6 | 26.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISO7640FM | |||||||
ICC1 | Disable | EN = 0 V | 0.35 | 0.7 | mA | ||
ICC2 | 4.5 | 6.6 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
0.4 | 0.8 | |||
ICC2 | 4.6 | 6.7 | |||||
ICC1 | 10 Mbps | 0.7 | 1.2 | ||||
ICC2 | 6.6 | 10.5 | |||||
ICC1 | 25 Mbps | 1.1 | 2 | ||||
ICC2 | 9.7 | 14.7 | |||||
ICC1 | 150 Mbps | 5 | 8.5 | ||||
ICC2 | 35 | 58 | |||||
ISO7641FM | |||||||
ICC1 | Disable | EN1 = EN2 = 0 V | 1.9 | 2.9 | mA | ||
ICC2 | 4.2 | 6.8 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
2 | 3 | |||
ICC2 | 4.3 | 6.9 | |||||
ICC1 | 10 Mbps | 2.5 | 3.5 | ||||
ICC2 | 6 | 8.2 | |||||
ICC1 | 25 Mbps | 3.4 | 4.5 | ||||
ICC2 | 8.8 | 11.4 | |||||
ICC1 | 150 Mbps | 10.5 | 14.5 | ||||
ICC2 | 31 | 42 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISO7640FM | |||||||
ICC1 | Disable | EN = 0 V | 0.35 | 0.7 | mA | ||
ICC2 | 3.6 | 5.1 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
0.4 | 0.8 | |||
ICC2 | 3.7 | 5.2 | |||||
ICC1 | 10 Mbps | 0.7 | 1.2 | ||||
ICC2 | 5 | 7.1 | |||||
ICC1 | 25 Mbps | 1.1 | 2 | ||||
ICC2 | 6.9 | 11 | |||||
ICC1 | 150 Mbps | 5 | 8.5 | ||||
ICC2 | 24 | 40 | |||||
ISO7641FM | |||||||
ICC1 | Disable | EN1 = EN2 = 0 V | 1.9 | 2.9 | mA | ||
ICC2 | 3.2 | 4.9 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
2 | 3 | |||
ICC2 | 3.3 | 5 | |||||
ICC1 | 10 Mbps | 2.5 | 3.5 | ||||
ICC2 | 4.4 | 5.8 | |||||
ICC1 | 25 Mbps | 3.4 | 4.5 | ||||
ICC2 | 6.1 | 7.6 | |||||
ICC1 | 150 Mbps | 10.5 | 14.5 | ||||
ICC2 | 20.6 | 26.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISO7640FM | |||||||
ICC1 | Disable | EN = 0 V | 0.2 | 0.6 | mA | ||
ICC2 | 3.3 | 5 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
0.2 | 0.7 | |||
ICC2 | 3.4 | 5.1 | |||||
ICC1 | 10 Mbps | 0.4 | 1.1 | ||||
ICC2 | 4.4 | 6.8 | |||||
ICC1 | 25 Mbps | 0.8 | 1.8 | ||||
ICC2 | 6 | 9.5 | |||||
ICC1 | 100 Mbps | 2.7 | 5 | ||||
ICC2 | 14.2 | 21 | |||||
ISO7641FM | |||||||
ICC1 | Disable | EN1 = EN2 = 0 V | 1.6 | 2.4 | mA | ||
ICC2 | 2.8 | 4.1 | |||||
ICC1 | DC to 1 Mbps | DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF |
1.7 | 2.5 | |||
ICC2 | 2.9 | 4.2 | |||||
ICC1 | 10 Mbps | 2.1 | 3 | ||||
ICC2 | 3.8 | 5 | |||||
ICC1 | 25 Mbps | 2.8 | 3.8 | ||||
ICC2 | 5.2 | 6.7 | |||||
ICC1 | 100 Mbps | 6.4 | 7.5 | ||||
ICC2 | 11.8 | 15.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 9 | 3.5 | 7 | 10.5 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2 | |||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 2 | ||||
Opposite-direction Channels | 3 | ||||||
tsk(pp)(3) | Part-to-part skew time | 4.5 | |||||
tr | Output signal rise time | See Figure 9 | 1.6 | ns | |||
tf | Output signal fall time | 1 | |||||
tPHZ | Disable Propagation Delay, high-to-high impedance output | See Figure 10 | 5 | 16 | ns | ||
tPLZ | Disable Propagation Delay, low-to-high impedance output | 5 | 16 | ||||
tPZH | Enable Propagation Delay, high impedance-to-high output | 4 | 16 | ||||
tPZL | Enable Propagation Delay, high impedance-to-low output | 4 | 16 | ||||
tfs | Fail-safe output delay time from input data or power loss | See Figure 11 | 9.5 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 9 | 4 | 8 | 13 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2 | |||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 2.5 | ||||
Opposite-direction Channels | 3.5 | ||||||
tsk(pp)(3) | Part-to-part skew time | 6 | |||||
tr | Output signal rise time | See Figure 9 | 2 | ns | |||
tf | Output signal fall time | 1.2 | |||||
tPHZ | Disable Propagation Delay, high-to-high impedance output | See Figure 10 | 6.5 | 17 | ns | ||
tPLZ | Disable Propagation Delay, low-to-high impedance output | 6.5 | 17 | ||||
tPZH | Enable Propagation Delay, high impedance-to-high output | 5.5 | 17 | ||||
tPZL | Enable Propagation Delay, high impedance-to-low output | 5.5 | 17 | ||||
tfs | Fail-safe output delay time from input data or power loss | See Figure 11 | 9.5 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 9 | 4 | 7.5 | 12.5 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2 | |||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 2.5 | ||||
Opposite-direction Channels | 3.5 | ||||||
tsk(pp)(3) | Part-to-part skew time | 6 | |||||
tr | Output signal rise time | See Figure 9 | 1.7 | ns | |||
tf | Output signal fall time | 1.1 | |||||
tPHZ | Disable Propagation Delay, high-to-high impedance output | See Figure 10 | 5.5 | 17 | ns | ||
tPLZ | Disable Propagation Delay, low-to-high impedance output | 5.5 | 17 | ||||
tPZH | Enable Propagation Delay, high impedance-to-high output | 4.5 | 17 | ||||
tPZL | Enable Propagation Delay, high impedance-to-low output | 4.5 | 17 | ||||
tfs | Fail-safe output delay time from input data or power loss | See Figure 11 | 9.5 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 9 | 4 | 8.5 | 14 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2 | |||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 3 | ||||
Opposite-direction Channels | 4 | ||||||
tsk(pp)(3) | Part-to-part skew time | 6.5 | |||||
tr | Output signal rise time | See Figure 9 | 2 | ns | |||
tf | Output signal fall time | 1.3 | |||||
tPHZ | Disable Propagation Delay, high-to-high impedance output | See Figure 10 | 6.5 | 17 | ns | ||
tPLZ | Disable Propagation Delay, low-to-high impedance output | 6.5 | 17 | ||||
tPZH | Enable Propagation Delay, high impedance-to-high output | 5.5 | 17 | ||||
tPZL | Enable Propagation Delay, high impedance-to-low output | 5.5 | 17 | ||||
tfs | Fail-safe output delay time from input data or power loss | See Figure 11 | 9.2 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 9 | 5 | 8 | 16 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | |||||
tsk(o)(2) | Channel-to-channel output skew time | Same-direction Channels | 4 | ||||
Opposite-direction Channels | 5 | ||||||
tsk(pp)(3) | Part-to-part skew time | 8 | |||||
tr | Output signal rise time | See Figure 9 | 2.3 | ns | |||
tf | Output signal fall time | 1.8 | |||||
tPHZ | Disable Propagation Delay, high-to-high impedance output | See Figure 10 | 8 | 18 | ns | ||
tPLZ | Disable Propagation Delay, low-to-high impedance output | 8 | 18 | ||||
tPZH | Enable Propagation Delay, high impedance-to-high output | 7 | 18 | ||||
tPZL | Enable Propagation Delay, high impedance-to-low output | 7 | 18 | ||||
tfs | Fail-safe output delay time from input data or power loss | See Figure 11 | 8.5 | μs |