SPRS866G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
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The boot sequence is a process by which the internal memory is loaded with program and data sections. The boot sequence is started automatically after each power-on reset or warm reset.
The 66AK2Hxx supports several boot processes that begin execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. For more details on boot sequence, see the KeyStone II Architecture ARM Bootloader User's Guide.
For 66AK2Hxx nonsecure devices, there are two types of booting: the C66x CorePac as the boot master and the ARM CorePac as the boot master. For secure devices, the C66x CorePac is always the secure master and the C66x CorePac0 or ARM CorePac Core0 can be the boot master. The ARM CorePac does not support no-boot mode. Both the C66x CorePacs and the ARM CorePac need to read the BOOTMODE register to determine how to proceed with the boot.
Table 10-1 shows memory space reserved for boot by the C66x CorePac.
START ADDRESS | SIZE | DESCRIPTION |
---|---|---|
0x80_0000 | 0x1_0000 | Reserved |
0x8e_7f80 | 0x80 | C66x CorePac ROM version string |
0x8e_8000 | 0x7f00 | Boot Master Table overlayed with scratch |
0x8e_767c | 4 | Boot Master Table Valid Length Field |
0x8e_fff0 | 4 | Host Data Address (boot magic address for secure boot through master peripherals) |
0x8f_7800 | 0x410 | Secure host Data structure |
0x8f_a290 | 0x4000 | Boot Stack |
0x8f_e290 | 0x90 | Boot Log Data |
0x8f_e320 | 0x20 | Boot Status Stack |
0x8f_e410 | 0xf0 | Boot Stats |
0x8f_e520 | 0x13fc | Boot Data |
0x8f_f91c | 0x404 | Boot Trace Info |
0x8f_fd20 | 0x180 | DDR Config |
0x8f_fea0 | 0x60 | Boot RAM call table |
0x8f_ff00 | 0x80 | Boot Parameter table |
0x8f_fff8 | 0x4 | Secure Signal Magic address |
0x8f_fffc | 0x4 | Boot Magic address |
Table 10-2 shows addresses reserved for boot by the ARM CorePac.
START ADDRESS | SIZE | DESCRIPTION |
---|---|---|
0xc57_e000 | 0xc00 | Context RAM not scrubbed on secure boot |
0xc58_6f80 | 0x80 | Global level 0 nonsecure translation table |
0xc58_7000 | 0x5000 | Global nonsecure page table for memory covering ROM |
0xc58_c000 | 0x1000 | Core 0 nonsecure level 1 translation table |
0xc58_d000 | 0x1000 | Core 1 nonsecure level 1 translation table |
0xc58_e000 | 0x1000 | Core 2 nonsecure level 1 translation table |
0xc58_f000 | 0x1000 | Core 3 nonsecure level 1 translation table |
0xc59_0000 | 0x7f00 | Packet memory buffer |
0xc59_7f00 | 4 | Host Data Address (boot magic address for secure boot through master peripherals) |
0xc5a_6e00 | 0x200 | DDR3a configuration structure |
0xc5a_7000 | 0x3000 | Boot Data |
0xc5a_a000 | 0x3000 | Supervisor stack, each core gets 0xc00 bytes |
0xc5a_d000 | 4 | Arm boot magic address, core 0 |
0xc5a_d004 | 4 | Arm boot magic address, core 1 |
0xc5a_d008 | 4 | Arm boot magic address, core 2 |
0xc5a_d00c | 4 | Arm boot magic address, core 3 |
0xc5a_e000 | 0x400 | Abort stack, core 0 |
0xc5a_e400 | 0x400 | Abort stack, core 1 |
0xc5a_e800 | 0x400 | Abort stack, core 2 |
0xc5a_ec00 | 0x400 | Abort stack, core 3 |
0xc5a_f000 | 0x400 | Unknown mode stack, core 0 |
0xc5a_f400 | 0x400 | Unknown mode stack, core 1 |
0xc5a_f800 | 0x400 | Unknown mode stack, core 2 |
0xc5a_fc00 | 0x400 | Unknown mode stack, core 3 |
0xc5b_0000 | 0x180 | Boot Version string, core 0 |
0xc5b_0180 | 0x80 | Boot status stack, core 0 |
0xc5b_0200 | 0x100 | Boot stats, core 0 |
0xc5b_0300 | 0x100 | Boot log, core 0 |
0x5b_0400 | 0x100 | Boot RAM call table, core 0 |
0xc5b_0500 | 0x100 | Boot parameter tables, core 0 |
0xc5b_0600 | 0x19e0 | Boot Data, core 0 |
0xc5b_1fe0 | 0x1010 | Boot Trace, core 0 |
0xc5b_4000 | 0x180 | Boot Version string, core 1 |
0xc5b_4180 | 0x80 | Boot status stack, core 1 |
0xc5b_4200 | 0x100 | Boot stats, core 1 |
0xc5b_4300 | 0x100 | Boot log, core 1 |
0x5b_4400 | 0x100 | Boot RAM call table, core 1 |
0xc5b_4500 | 0x100 | Boot parameter tables, core 1 |
0xc5b_4600 | 0x19e0 | Boot Data, core 1 |
0xc5b_5fe0 | 0x1010 | Boot Trace, core 1 |
0xc5b_8000 | 0x180 | Boot Version string, core 2 |
0xc5b_8180 | 0x80 | Boot status stack, core 2 |
0xc5b_8200 | 0x100 | Boot stats, core 2 |
0xc5b_8300 | 0x100 | Boot log, core 2 |
0x5b_8400 | 0x100 | Boot RAM call table, core 2 |
0xc5b_8500 | 0x100 | Boot parameter tables, core 2 |
0xc5b_8600 | 0x19e0 | Boot Data, core 2 |
0xc5b_9fe0 | 0x1010 | Boot Trace, core 2 |
0xc5b_c000 | 0x180 | Boot Version string, core 3 |
0xc5b_c180 | 0x80 | Boot status stack, core 3 |
0xc5b_c200 | 0x100 | Boot stats, core 3 |
0xc5b_c300 | 0x100 | Boot log, core 3 |
0x5b_c400 | 0x100 | Boot RAM call table, core 3 |
0xc5b_c500 | 0x100 | Boot parameter tables, core 3 |
0xc5b_c600 | 0x19e0 | Boot Data, core 3 |
0xc5b_dfe0 | 0x1010 | Boot Trace, core 3 |
0xc5c_0000 | 0x4_0000 | Secure MSMC |
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are four possible boot modes:
After the Boot ROM for the Cortex-A15 processor reads the BOOTMODE to determine that the C66x CorePac is the boot master, all Cortex-A15 processors stay idle by executing WFI instruction and waiting for the C66x CorePac’s interrupt. The chip Boot ROM reads the BOOTMODE register to determine that the C66x CorePac0 is the boot master, then the C66x CorePac0 performs the boot process and the other C66x CorePacs execute an IDLE instruction. After the boot process is completed, the C66x CorePac0 begins to execute the code downloaded during the boot process. If the downloaded code included code for the other C66x cores and/or the Cortex-A15 processor cores, the downloaded code may contain logic to write the code execution addresses to the boot address register for the core that is to execute it. The C66x CorePac0 can then generate an interrupt to the core causing it to execute the code. When they receive the IPC interrupt, the rest of the C66x CorePacs and the ARM CorePac complete boot management operations and begin executing from the predefined location in memory.
The boot process performed by the C66x CorePac0 and the ARM CorePac Core0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[15:0] value in the DEVSTAT register. The C66x CorePac0 and the ARM CorePac Core0 read this value, and then execute the associated boot process in software. Bit 8 determines whether the boot is C66x CorePac boot or ARM CorePac boot. The figure below shows the bits associated with BOOTMODE[15:0] (DEVSTAT[16:1]) when the C66x CorePac or ARM CorePac is the boot master. Figure 10-1 does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select overall system endianess that is independent of the boot mode.
The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in Section 11.5.
NOTE
It is important to remember that the BOOTMODE[15:0] pins map to the DEVSTAT[16:1] bits of the DEVSTAT register.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | Mode |
X | X | 0 | ARMEN | SYSEN | ARM PLL CONFIG | Boot Master | SYS PLL CONFIG | Min | 0 | 0 | 0 | SLEEP | ||||
SlaveAddr | 1 | Port | 0 | 0 | 0 | I2C SLAVE | ||||||||||
X | X | X | Bus Addr | Param ldx | X | Port | 0 | 0 | 1 | I2C MASTER | ||||||
Width | Csel | Mode | Npin | 0 | 1 | 0 | SPI | |||||||||
0 | Base Addr | Wait | Width | ARM PLL CONFIG | SYS PLL CONFIG | 0 | 0 | 1 | 1 | EMIF (ARM Master) | ||||||
X | Chip Sel | EMIF (DSP Master) | ||||||||||||||
1 | First Block | Clear | ARM PLL CONFIG | Min | NAND (ARM Master) | |||||||||||
X | Chip Sel | NAND (DSP Master) | ||||||||||||||
Lane | Ref Clock | Data Rate | ARM PLL CONFIG | 1 | 0 | 0 | SRIO (ARM Master) | |||||||||
X | Lane Setup | SRIO (DSP Master) | ||||||||||||||
PA clk | Ref clk | Ext Con | ARM PLL CONFIG | 1 | 0 | 1 | Ethernet (ARM Master) | |||||||||
Rsvd | Lane Setup | Ethernet (DSP Master) | ||||||||||||||
Ref clk | Bar Config | ARM PLL CONFIG | 0 | 1 | 1 | 0 | PCIe (ARM Master) | |||||||||
SerDes Cfg | PCIe (DSP Master) | |||||||||||||||
Port | Ref clk | Data Rate | ARM PLL CONFIG | 1 | 1 | 1 | 0 | HyperLink (ARM Master) | ||||||||
SerDes Cfg | HyperLink (DSP Master) | |||||||||||||||
X | X | X | X | Port | ARM PLL CONFIG | Min | 1 | 1 | 1 | UART (ARM Master) | ||||||
X | X | X | X | X | X | X | UART (DSP Master) |
The Boot Device field BOOTMODE[16-14-4-3-2-1] bits define the boot device that is chosen and the BOOTMODE[8] bit defines the boot master that is chosen. Table 10-3 shows the supported boot modes.
Bit | Field | Description |
---|---|---|
16, 14, 4, 3, 2, 1 | Boot Device | Device boot mode
|
The device configuration fields DEVSTAT[16:1] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
X | X | 0 | ARMen | SYSEN | ARM PLL Cfg | Boot Master | Sys PLL Config | Min | 000 | Lendian |
Bit | Field | Description |
---|---|---|
16-15 | Reserved | Reserved |
14 | Boot Devices | Boot Device- used in conjunction with Boot Devices [Used in conjunction with bits 3-1]
|
13 | ARMen | Enable the ARM PLL
|
12 | SYSEN | Enable the System PLL
|
11-9 | ARM PLL Setting | The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices[3:1] used in conjunction with Boot Device [14]
|
0 | Lendian | Endianess (device)
|
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Slave Addr | 1 | Port | ARM PLL Cfg | Boot Master | Sys PLL Config | Min | 000 | Lendian |
Bit | Field | Description |
---|---|---|
16-15 | Slave Addr | I2C Slave boot bus address
|
14 | Boot Devices | Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1]
|
13-12 | Port | I2C port number
|
11-9 | ARM PLL Setting | The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices[3:1] used in conjunction with Boot Device [14]
|
0 | Lendian | Endianess
|
In master mode, the I2C device configuration uses 10 bits of device configuration instead of seven as used in other boot modes. In this mode, the device makes the initial read of the I2C EEPROM while the PLL is in bypass mode. The initial read contains the desired clock multiplier, which must be set up prior to any subsequent reads.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Bus Addr | Param ldx/Offset | Boot Master | Reserved | Port | Min | 001 | Lendian |
Bit | Field | Description |
---|---|---|
16-14 | Reserved | Reserved |
13-12 | Bus Addr | I2C bus address slave device
|
11-9 | Param Idx/Offset | Parameter Table Index: 0-7 This value specifies the parameter table index when the C66x is the boot master This value specifies the start read address at 8K times this value when the ARM is the boot master |
8 | Boot Master | Boot Master select
|
7 | Reserved |
|
6-5 | Port | I2C port number
|
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices[3:1]
|
0 | Lendian | Endianess
|
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Width | Csel | Mode | Param ldx/Offset | Boot Master | Npin | Port | Min | 010 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Width | SPI address width configuration
|
15-14 | Csel | The chip select field value 0-3 (default = 0) |
13-12 | Mode | Clk Polarity/ Phase
|
11-9 | Param Idx/Offset | Parameter Table Index: 0-7 This value specifies the parameter table index when the C66x is the boot master This value specifies the start read address at 8K times this value when the ARM is the boot master |
8 | Boot Master | Boot Master select
|
7 | Npin | Selected Chip Select driven
|
6-5 | Port | Specify SPI port
|
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices[3:1]
|
0 | Lendian | Endianess
|
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Base Addr | Wait | Width | X | Chip Sel | Boot Master=1 | Sys PLL Cfg | 0 | 011 | Lendian | ||||||
0 | Base Addr | Wait | Width | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | 0 | 011 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Boot Devices | Boot Devices[16] used conjunction with Boot Devices[4] and Boot Devices [Used in conjunction with bits 3-1]
|
15-14 | Base Addr | Base address (0-3) used to calculate the branch address. Branch address is the chip select plus Base Address *16MB |
13 | Wait | Extended Wait
|
12 | Width | EMIF Width
|
11-9 | Chip Sel/ARM PLL Setting | When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS0 is used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region, CS0-CS3.
|
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
4 | Boot Devices | Boot Devices[4] used conjunction with Boot Devices[16] and Boot Devices [Use din conjunction with bits 3-1]
|
3-1 | Boot Devices | Boot Devices[3:1] used in conjunction with Boot Device [4]
|
0 | Lendian | Endianess
|
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | First Block | Clear | X | Chip Sel | Boot Master=1 | Sys PLL Cfg | Min | 011 | Lendian | |||||||
1 | First Block | Clear | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | Min | 011 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Boot Devices | Boot Devices[16] used conjunction with Boot Devices [3-1]
|
15-13 | First Block | First Block. This value is used to calculate the first block read. The first block read is the first block value *16. |
12 | Clear | ClearNAND
|
11-9 | Chip Sel/ARM PLL Setting | When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS2 is used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region, CS2-CS5.
|
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
4 | Min | Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that would normally be set by the other BOOTMODE pins when Min is 0.
|
3-1 | Boot Devices | Boot Devices
|
0 | Lendian | Endianess
|
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
X | Ref Clock | Data Rate | Lane Setup | Boot Master=1 | Sys PLL Cfg | Min | 100 | Lendian | ||||||||
Lane | Ref Clock | Data Rate | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | Min | 100 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Lane | When Boot Master =0 (ARM is Boot Master), Pin[16] is used as Lane.
When Boot Master =1 (C66x is Boot Master), Pin[16] is reserved. |
15-14 | Ref Clock | SRIO Reference clock frequency
|
13-12 | Data Rate | SRIO Data Rate
|
11-9 | Lane Setup/ARM PLL Setting | When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting with all lanes enabled. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. The default value is 156.26 MHz. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [11:9] are used as Lane Set up.
|
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 10-27 shows settings for various input clock frequencies. (default = 4) |
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices
|
0 | Lendian | Endianess
|
In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Pa clk | Ref Clock | Ext Con | Lane Setup | Boot Master=1 | Sys PLL Cfg | Min | 101 | Lendian | ||||||||
Pa clk | Ref Clock | Ext Con | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | Min | 101 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Pa clk | PA clock reference
|
15-14 | Ref Clock | SRIO Reference clock frequency
|
13-12 | Ext Con | External connection mode
|
11-9 | Lane Setup/ARM PLL Setting | When Boot Master = 0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are used as Lane Set up.
|
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 10-27 shows settings for various input clock frequencies. (default = 4) |
4 | Min | Minimum boot configuration select bit.
When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices
|
0 | Lendian | Endianess
|
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Ref clk | Bar Config | Reserved | Boot Master=1 | Sys PLL Cfg | 0110 | Lendian | ||||||||||
Ref clk | Bar Config | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | 0110 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Ref clk | PCIe Reference clock frequency
|
15-12 | Bar Config | PCIe BAR registers configuration This value can range from 0 to 0xf. See Table 10-13. |
11-9 | Reserved/ARM PLL Setting | When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved. |
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 10-27 shows settings for various input clock frequencies. |
4-1 | Boot Devices | Boot Devices[4:1]
|
0 | Lendian | Endianess
|
BAR CFG | BAR0 | 32-BIT ADDRESS TRANSLATION | 64-BIT ADDRESS TRANSLATION | |||||
---|---|---|---|---|---|---|---|---|
BAR1 | BAR2 | BAR3 | BAR4 | BAR5 | BAR2/3 | BAR4/5 | ||
0b0000 | PCIe MMRs | 32 | 32 | 32 | 32 | Clone of BAR4 | ||
0b0001 | 16 | 16 | 32 | 64 | ||||
0b0010 | 16 | 32 | 32 | 64 | ||||
0b0011 | 32 | 32 | 32 | 64 | ||||
0b0100 | 16 | 16 | 64 | 64 | ||||
0b0101 | 16 | 32 | 64 | 64 | ||||
0b0110 | 32 | 32 | 64 | 64 | ||||
0b0111 | 32 | 32 | 64 | 128 | ||||
0b1000 | 64 | 64 | 128 | 256 | ||||
0b1001 | 4 | 128 | 128 | 128 | ||||
0b1010 | 4 | 128 | 128 | 256 | ||||
0b1011 | 4 | 128 | 256 | 256 | ||||
0b1100 | 256 | 256 | ||||||
0b1101 | 512 | 512 | ||||||
0b1110 | 1024 | 1024 | ||||||
0b1111 | 2048 | 2048 |
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Port | RefClk | Data Rate | Reserved | Boot Master=1 | Sys PLL Cfg | 1110 | Lendian | |||||||||
Port | RefClk | Data Rate | ARM PLL Cfg | Boot Master=0 | Sys PLL Cfg | 1110 | Lendian |
Bit | Field | Description |
---|---|---|
16 | Port | HyperLink port
|
15-14 | Ref Clocks | HyperLink reference clock configuration
|
13-12 | Data Rate | HyperLink data rate configuration
|
11-9 | Reserved/ARM PLL Setting | When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved. |
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 10-27 shows settings for various input clock frequencies. |
4-1 | Boot Devices | Boot Devices[4:1]
|
0 | Lendian | Endianess
|
DEVSTAT Boot Mode Pins ROM Mapping | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
X | X | X | X | Port | X | X | X | Boot Master=1 | Sys PLL Config | Min | 111 | Lendian | ||||
X | X | X | X | Port | ARM PLL Cfg | Boot Master=0 | Sys PLL Config | Min | 111 | Lendian |
Bit | Field | Description |
---|---|---|
16-13 | Reserved | Not Used |
12 | Port | UART Port number
|
11-9 | ARM PLL Setting | The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. |
8 | Boot Master | Boot Master select
|
7-5 | SYS PLL Setting | The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 10-27 shows settings for various input clock frequencies. (default = 4) |
4 | Min | Minimum boot configuration select bit.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured. |
3-1 | Boot Devices | Boot Devices[3:1]
|
0 | Lendian | Endianess
|
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the most common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common entries in the boot parameter table are shown in Table 10-16.
BYTE OFFSET | NAME | DESCRIPTION |
---|---|---|
0 | Length | The length of the table, including the length field, in bytes. |
2 | Checksum | The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification of the table by the boot ROM. |
4 | Boot Mode | Internal values used by RBL for different boot modes. |
6 | Port Num | Identifies the device port number to boot from, if applicable |
8 | SW PLL, MSW | PLL configuration, MSW |
10 | SW PLL, LSW | PLL configuration, LSW |
12 | Sec PLL Config, MSW | ARM PLL configuration, MSW |
14 | Sec PLL Config, LSW | ARM PLL configuration, LSW |
16 | System Freq | The frequency of the system clock in MHz |
18 | Core Freq | The frequency of the core clock in MHz |
20 | Boot Master | Set to TRUE if C66x is the master core. |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Async Config Parameters are used.
|
NO |
24 | Type | Set to 0 for EMIF16 (NOR) boot | NO |
26 | Branch Address MSW | Most significant bit for Branch address (depends on chip select) | YES |
28 | Branch Address LSW | Least significant bit for Branch address (depends on chip select) | YES |
30 | Chip Select | Chip Select for the NOR flash | YES |
32 | Memory Width | Memory width of the EMIF16 bus (16 bits) | YES |
34 | Wait Enable | Extended wait mode enabled
|
YES |
36 | Async Config MSW | Async Config Register MSW | NO |
38 | Async Config LSW | Async Config Register LSW | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Bit 0 Tx enable
Bit 1 Mailbox Enable
Bit 2 Bypass Configuration
Bit 3 Bypass QM Configuration
Bit 4 PLL setup
Bit 5-15 = Reserved |
NO |
24 | Lane Setup |
|
YES (but not all lane setup are possible through the boot configuration pins) |
26 | Reserved | Reserved | NA |
28 | Node ID | The node ID value to set for this device | NO |
30 | SerDes ref clk | The SerDes reference clock frequency, in 1/100 MHZ | YES |
32 | Link Rate | Link rate, MHz | YES |
34 | PF Low | Packet forward address range, low value | NO |
36 | PF High | Packet Forward address range, high value | NO |
38 | Promiscuous Mask | The bit is set for each lane/port that is configured as promiscuous | NO |
40 | Time-out Sec | Number of seconds before time-out. The value 0 disables the time-out. | NO |
44 | SERDES Aux, MSW | SERDES Auxillary Register Configuration, MSW | NO |
48 | SERDES Aux, LSW | SERDES Auxillary Register Configuration, LSW | NO |
52 | SERDES Rx Lane0 MSW | SERDES Rx Configuration, Lane0, MSW | NO |
56 | SERDES Rx Lane0 LSW | SERDES Rx Configuration, Lane0, LSW | NO |
60 | SERDES Rx Lane1 MSW | SERDES Rx Configuration, Lane1, MSW | NO |
64 | SERDES Rx Lane1 LSW | SERDES Rx Configuration, Lane1, LSW | NO |
68 | SERDES Rx Lane2 MSW | SERDES Rx Configuration, Lane2, MSW | NO |
72 | SERDES Rx Lane2 LSW | SERDES Rx Configuration, Lane2, LSW | NO |
76 | SERDES Rx Lane3 MSW | SERDES Rx Configuration, Lane3, MSW | NO |
80 | SERDES Rx Lane3 LSW | SERDES Rx Configuration, Lane3, LSW | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Bits 02-00 Interface
Bits 03 HD
Bit 4 Skip TX
Bits 06-05 Initialize Config
Bits 15-07 Reserved |
NO |
24 | MAC High | The 16 MSBs of the MAC address to receive during boot | NO |
26 | MAC Med | The 16 middle bits of the MAC address to receive during boot | NO |
28 | MAC Low | The 16 LSBs of the MAC address to receive during boot | NO |
30 | Multi MAC High | The 16 MSBs of the multicast MAC address to receive during boot | NO |
32 | Multi MAC Med | The 16 middle bits of the multicast MAC address to receive during boot | NO |
34 | Multi MAC Low | The 16 LSBs of the multicast MAC address to receive during boot | NO |
36 | Source Port | The source UDP port to accept boot packets from. A value of 0 will accept packets from any UDP port |
NO |
38 | Dest Port | The destination port to accept boot packets on. | NO |
40 | Device ID 12 | The first 2 bytes of the device ID. This is typically a string value, and is sent in the Ethernet ready frame |
NO |
42 | Device ID 34 | The second 2 bytes of the device ID. | NO |
44 | Dest MAC High | The 16 MSBs of the MAC destination address used for the Ethernet ready frame. Default is broadcast. |
NO |
46 | Dest MAC Med | The 16 middle bits of the MAC destination address | NO |
48 | Dest MAC Low | The 16 LSBs of the MAC destination address | NO |
50 | Lane Enable | One bit per lane.
|
|
52 | SGMII Config | Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if no configuration done | NO |
54 | SGMII Control | The SGMII control register value | NO |
56 | SGMII Adv Ability | The SGMII ADV Ability register value | NO |
58 | SGMII TX Cfg High | The 16 MSBs of the SGMII Tx config register | NO |
60 | SGMII TX Cfg Low | The 16 LSBs of the SGMII Tx config register | NO |
62 | SGMII RX Cfg High | The 16 MSBs of the SGMII Rx config register | NO |
64 | SGMII RX Cfg Low | The 16 LSBs of the SGMII Rx config register | NO |
66 | SGMII Aux Cfg High | The 16 MSBs of the SGMII Aux config register | NO |
68 | SGMII Aux Cfg Low | The 16 LSBs of the SGMII Aux config register | NO |
70 | PKT PLL Cfg MSW | The packet subsystem PLL configuration, MSW | NO |
72 | PKT PLL CFG LSW | The packet subsystem PLL configuration, LSW | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Bits 00 Mode
Bits 01 Configuration of PCIe
Bit 03-02 Reserved Bits 04 Multiplier
Bits 05-15 Reserved |
NO |
24 | Address Width | PCI address width, can be 32 or 64 | YES with in conjunction with BAR sizes |
26 | Link Rate | SerDes frequency, in Mbps. Can be 2500 or 5000 | NO |
28 | Reference clock | Reference clock frequency, in units of 10 kHz. Value values are 10000 (100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz) and 31250 (312.5 MHz). A value of 0 means that value is already in the SerDes cfg parameters and will not be computed by the boot ROM. | NO |
30 | Window 1 Size | Window 1 size. | YES |
32 | Window 2 Size | Window 2 size. | YES |
34 | Window 3 Size | Window 3 size. Valid only if address width is 32. | YES |
36 | Window 4 Size | Window 4 Size. Valid only if the address width is 32. | YES |
38 | Vendor ID | Vendor ID | NO |
40 | Device ID | Device ID | NO |
42 | Class code Rev ID MSW | Class code revision ID MSW | NO |
44 | Class code Rev ID LSW | Class code revision ID LSW | NO |
46 | SerDes cfg msw | PCIe SerDes config word, MSW | NO |
48 | SerDes cfg lsw | PCIe SerDes config word, LSW | NO |
50 | SerDes lane 0 cfg msw | SerDes lane config word, msw lane 0 | NO |
52 | SerDes lane 0 cfg lsw | SerDes lane config word, lsw, lane 0 | NO |
54 | SerDes lane 1 cfg msw | SerDes lane config word, msw, lane 1 | NO |
56 | SerDes lane 1 cfg lsw | SerDes lane config word, lsw, lane 1 | NO |
58 | Time-out period (Secs) | The time-out period. Values 0 disables the time-out. |
OFFSET | FIELD | VALUE | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Option | Bits 02-00 Mode
Bits 15-03 Reserved |
NO |
24 | Boot Dev Addr | The I2C device address to boot from | YES |
26 | Boot Dev Addr Ext | Extended boot device address | YES |
28 | Broadcast Addr | I2C address used to send data in the I2C master broadcast mode. | NO |
30 | Local Address | The I2C address of this device | NO |
34 | Bus Frequency | The desired I2C data rate (kHz) | NO |
36 | Next Dev Addr | The next device address to boot (Used only if boot config option is selected) | NO |
38 | Next Dev Addr Ext | The extended next device address to boot (Used only if boot config option is selected) | NO |
40 | Address Delay | The number of CPU cycles to delay between writing the address to an I2C EEPROM and reading data. | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Bits 01 and 00 Modes
|
NO |
24 | Address Width | The number of bytes in the SPI device address. Can be 16 or 24 bit | YES |
26 | NPin | The operational mode, 4 or 5 pin | YES |
28 | Chipsel | The chip select used (valid in 4 pin mode only). Can be 0-3. | YES |
30 | Mode | Standard SPI mode (0-3) | YES |
32 | C2Delay | Setup time between chip assert and transaction | NO |
34 | Bus Freq, 100kHz | The SPI bus frequency in kHz. | NO |
36 | Read Addr MSW | The first address to read from, MSW (valid for 24 bit address width only) | YES |
38 | Read Addr LSW | The first address to read from, LSW | YES |
40 | Next Chip Select | Next Chip Select to be used (Used only in boot Config mode) | NO |
42 | Next Read Addr MSW | The Next read address (used in boot config mode only) | NO |
44 | Next Read Addr LSW | The Next read address (used in boot config mode only) | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
12 | Options | Bits 00 Reserved Bits 01 Configuration of Hyperlink
|
NO |
14 | Number of Lanes | Number of Lanes to be configured | NO |
16 | SerDes cfg msw | PCIe SerDes config word, MSW | NO |
18 | SerDes cfg lsw | PCIe SerDes config word, LSW | NO |
20 | SerDes CFG RX lane 0 cfg msw | SerDes RX lane config word, msw lane 0 | NO |
22 | SerDes CFG RXlane 0 cfg lsw | SerDes RX lane config word, lsw, lane 0 | NO |
24 | SerDes CFG TX lane 0 cfg msw | SerDes TX lane config word, msw lane 0 | NO |
26 | SerDes CFG TXlane 0 cfg lsw | SerDes TX lane config word, lsw, lane 0 | NO |
28 | SerDes CFG RX lane 1 cfg msw | SerDes RX lane config word, msw lane 1 | NO |
30 | SerDes CFG RXlane 1 cfg lsw | SerDes RX lane config word, lsw, lane 1 | NO |
32 | SerDes CFG TX lane 1 cfg msw | SerDes TX lane config word, msw lane 1 | NO |
34 | SerDes CFG TXlane 1 cfg lsw | SerDes TX lane config word, lsw, lane 1 | NO |
36 | SerDes CFG RX lane 2 cfg msw | SerDes RX lane config word, msw lane 2 | NO |
38 | SerDes CFG RXlane 2 cfg lsw | SerDes RX lane config word, lsw, lane 2 | NO |
40 | SerDes CFG TX lane 2 cfg msw | SerDes TX lane config word, msw lane 2 | NO |
42 | SerDes CFG TXlane 2 cfg lsw | SerDes TX lane config word, lsw, lane 2 | NO |
44 | SerDes CFG RX lane 3 cfg msw | SerDes RX lane config word, msw lane 3 | NO |
46 | SerDes CFG RXlane 3 cfg lsw | SerDes RX lane config word, lsw, lane 3 | NO |
48 | SerDes CFG TX lane 3 cfg msw | SerDes TX lane config word, msw lane 3 | NO |
50 | SerDes CFG TXlane 3 cfg lsw | SerDes TX lane config word, lsw, lane 3 | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Reserved | None | NA |
24 | Data Format | Bits 00 Data Format
|
NO |
26 | Protocol | Bits 00 Protocol
|
NO |
28 | Initial NACK Count | Number of NACK pings to be sent before giving up | NO |
30 | Max Err Count | Maximum number of consecutive receive errors acceptable. | NO |
32 | NACK Time-out | Time (ms) waiting for NACK/ACK. | NO |
34 | Character Time-out | Time Period between characters | NO |
36 | nDatabits | Number of bits supported for data. Only 8 bits is supported. | NO |
38 | Parity | Bits 01-00 Parity
|
NO |
40 | nStopBitsx2 | Number of stop bits times two. Valid values are 2 (stop bits = 1), 3 (Stop Bits = 1.5), 4 (Stop Bits = 2) | NO |
42 | Over sample factor | The over sample factor. Only 13 and 16 are valid. | NO |
44 | Flow Control | Bits 00 Flow Control
|
NO |
46 | Data Rate MSW | Baud Rate, MSW | NO |
48 | Data Rate LSW | Baud Rate, LSW | NO |
BYTE OFFSET | NAME | DESCRIPTION | CONFIGURED THROUGH BOOT CONFIGURATION PINS |
---|---|---|---|
22 | Options | Bits 00 Geometry
|
NO |
24 | numColumnAddrBytes | Number of bytes used to specify column address | NO |
26 | numRowAddrBytes | Number of bytes used to specify row address. | NO |
28 | numofDataBytesperPage_msw | Number of data bytes in each page, MSW | NO |
30 | numofDataBytesperPage_lsw | Number of data bytes in each page, LSW | NO |
32 | numPagesperBlock | Number of Pages per Block | NO |
34 | busWidth | EMIF bus width. Only 8 or 16 bits is supported. | NO |
36 | numSpareBytesperPage | Number of spare bytes allocated per page. | NO |
38 | csel | Chip Select number (valid chip selects are 2-5) | YES (If ARM is the boot master only chip select 2 is supported) |
40 | First Block | First block for RBL to try to read. | YES |
The RBL also provides an option to configure the DDR table before loading the image into the external memory. More information on how to configure the DDR3, see the KeyStone Architecture DSP Bootloader User's Guide. The configuration table for DDR3 is shown in Table 10-26
BYTE OFFSET | NAME | DESCRIPTION |
---|---|---|
0 | Enable bitmap MSW | Bits 31:0 of the PLL/EMIF enable bitmap. Bit 0 corresponds to the PLL config, Bit 1 to the SDRAM configuration register. There are 24 valid bits in this field (with the MSB corresponding to Rw/exc thresh). |
4 | Enable bitmap SLSW | Bits 31:0 of the chip level register enable bit map. Bit 0 corresponds to chip level configuration register 0. |
8 | Enable bitmap LSW | Bits 60:32 of the chip level register enable bit map. Bit 0 corresponds to chip level configuration register 32. |
12 | PLL Predivier | PLL Predivision (1 = divide by 1, 2 = divide by 2, and so on) |
16 | PLL Multiplier | PLL Multiplication |
20 | PLL Post Divider | PLL Postdivision |
24 | sdRamConfig | SDRAM Configuration Register |
28 | Refresh ctl | SDRAM Refresh Control Register |
32 | Timing 1 | SDRAM Timing 1 Register |
36 | Timing 2 | SDRAM Timing 2 Register |
40 | Timing 3 | SDRAM Timing 3 Register |
44 | Timing4 | SDRAM Timing 4 Register |
48 | Pwr management | Power Management Control Register |
52 | Vbus M cfg | VBUS M Configuration |
56 | Vbus M cfg val 1 | VBUS M Configuration Value 1 |
60 | Vbus M cfg val 2 | VBUSM Configuration Value 2 |
64 | IO DFT Test | I/O DFT test logic control |
68 | Perf ctl sel | Performance Counter Master Region Select Register |
72 | Perf cnt Mst Reg | Performance Count Master Region Select |
76 | Zq config | SDRAM Output Impedance Calibration Configuration Register |
80 | Pri Class Svc Map | Priority class Service Map |
84 | Mst Id class 1 | Master ID class service map 1 |
88 | Mst Id class 2 | Master ID class service map 2 |
92 | ECC ctrl | ECC Control Register |
96 | ECC addr rng 1 | ECC Address Range 1 Register |
100 | ECC addr rng 2 | ECC Address Range 2 Register |
104 | Rw/exc thresh | Read Write Execution Threshold Register |
108 | PHY PIR | PHY PIR register (SLSW mask bit 0) |
112 | PHY PGCR0 | PHY PGCR0 register (SLSW mask bit 1) |
116 | PHY PGCR1 | PHY PGCR1 register (SLSW mask bit 2) |
120 | PHY PGCR2 | PHY PGCR2 register (SLSW mask bit 3) |
124 | PHY PGSR0 | PHY PGSR0 register (SLSW mask bit 4) |
128 | PHY PGSR1 | PHY PGSR1 register (SLSW mask bit 5) |
132 | PHY PTR0 | PHY PTR 0 register (SLSW mask bit 6) |
136 | PHY PTR1 | PHY PTR 1 register (SLSW mask bit 7) |
140 | PHY PTR2 | PHY PTR 2 register (SLSW mask bit 8) |
144 | PHY PTR3 | PHY PTR 3 register (SLSW mask bit 9) |
148 | PHY PTR4 | PHY PTR 4 register (SLSW mask bit 10) |
152 | PHY DCR | PHY DCR register (SLSW mask bit 11) |
156 | PHY DTPR0 | PHY DTPR 0 register (SLSW mask bit 12) |
160 | PHY DTPR1 | PHY DTPR 1 register (SLSW mask bit 13) |
164 | PHY DTPR2 | PHY DTPR 2 register (SLSW mask bit 14) |
168 | PHY MR0 | PHY MR 0 register (SLSW mask bit 15) |
172 | PHY MR1 | PHY MR 1 register (SLSW mask bit 16) |
176 | PHY MR2 | PHY MR 2 register (SLSW mask bit 17) |
180 | PHY DTCR | PHY DTCR register (SLSW mask bit 18) |
184 | PHY DX0GCR | PHY DX 0 GCR register (SLSW mask bit 19) |
188 | PHY DX1GCR | PHY DX 1 GCR register (SLSW mask bit 20) |
192 | PHY DX2GCR | PHY DX 2 GCR register (SLSW mask bit 21) |
196 | PHY DX3GCR | PHY DX 3 GCR register (SLSW mask bit 22) |
200 | PHY DX4CGR | PHY DX 4 GCR register (SLSW mask bit 23) |
204 | PHY DX5GCR | PHY DX 5 GCR register (SLSW mask bit 24) |
208 | PHY DX6GCR | PHY DX 6 GCR register (SLSW mask bit 25) |
212 | PHY DX7GCR | PHY DX 7 GCR register (SLSW mask bit 26) |
216 | PHY DX8GCR | PHY DX 8 GCR register (SLSW mask bit 27) |
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for:
The TI SoC contains security architecture that allows the C66x CorePacs and ARM CorePac to perform secure accesses within the device. For more information, contact a TI sales office for additional information available with the purchase of a secure device.
The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 10-27 shows the settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See Table 10-11 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to reduce the frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The ARM CorePac PLL, DDR3A PLL, DDR3BPLL, and PASS PLL are controlled by chip level MMRs. For details on how to set up the PLL see Section 11.5. For details on the operation of the PLL controller module, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.
BOOTMODE [7:5] | INPUT CLOCK FREQ (MHz)(3) | 800-MHz DEVICE | 1000-MHz DEVICE | 1200-MHz DEVICE | PA = 350 MHz(1) | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLD | PLLM | DSP ƒ | PLLD | PLLM | DSP ƒ | PLLD | PLLM | DSP ƒ | PLLD | PLLM | DSP ƒ(2) | ||
0b000 | 50.00 | 0 | 31 | 800 | 0 | 39 | 1000 | 0 | 47 | 1200 | 0 | 41 | 1050 |
0b001 | 66.67 | 0 | 23 | 800.04 | 0 | 29 | 1000.05 | 0 | 35 | 1200.06 | 1 | 62 | 1050.053 |
0b010 | 80.00 | 0 | 19 | 800 | 0 | 24 | 1000 | 0 | 29 | 1200 | 3 | 104 | 1050 |
0b011 | 100.00 | 0 | 15 | 800 | 0 | 19 | 1000 | 0 | 23 | 1200 | 0 | 20 | 1050 |
0b100 | 156.25 | 3 | 40 | 800.78 | 4 | 63 | 1000 | 2 | 45 | 1197.92 | 24 | 335 | 1050 |
0b101 | 250.00 | 4 | 31 | 800 | 0 | 7 | 1000 | 4 | 47 | 1200 | 4 | 41 | 1050 |
0b110 | 312.50 | 7 | 40 | 800.78 | 4 | 31 | 1000 | 2 | 22 | 1197.92 | 24 | 167 | 1050 |
0b111 | 122.88 | 0 | 12 | 798.72 | 3 | 64 | 999.989 | 0 | 19 | 1228.80 | 11 | 204 | 1049.6 |
The PLL default settings are determined by the BOOTMODE[11:9] bits. Table 10-28 shows settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
The ARM CorePac PLL is controlled using a PLL controller and a chip-level MMR. For details on how to set up the PLL see Section 11.5. For details on the operation of the PLL controller module, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide.
BOOTMODE [11:9] | INPUT CLOCK FREQ (MHz)(2) | 800-MHz DEVICE | 1000-MHz DEVICE | 1200-MHz DEVICE | 1400-MHz DEVICE | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLD | PLLM | ARM ƒ | PLLD | PLLM | ARM ƒ | PLLD | PLLM | ARM ƒ | PLLD | PLLM | ARM ƒ(1) | ||
0b000 | 50.00 | 0 | 31 | 800 | 0 | 39 | 1000 | 0 | 47 | 1200 | 0 | 55 | 1400 |
0b001 | 66.67 | 0 | 23 | 800.04 | 0 | 29 | 1000.05 | 0 | 35 | 1200.06 | 0 | 41 | 1400.07 |
0b010 | 80.00 | 0 | 19 | 800 | 0 | 24 | 1000 | 0 | 29 | 1200 | 0 | 34 | 1400 |
0b011 | 100.00 | 0 | 15 | 800 | 0 | 19 | 1000 | 0 | 23 | 1200 | 0 | 27 | 1400 |
0b100 | 156.25 | 3 | 40 | 800.78 | 4 | 63 | 1000 | 2 | 45 | 1197.92 | 0 | 17 | 1406.25 |
0b101 | 250.00 | 4 | 31 | 800 | 0 | 7 | 1000 | 4 | 47 | 1200 | 4 | 55 | 1400 |
0b110 | 312.50 | 7 | 40 | 800.78 | 4 | 31 | 1000 | 2 | 22 | 1197.92 | 0 | 8 | 1406.25 |
0b111 | 122.88 | 0 | 12 | 798.72 | 3 | 64 | 999.40 | 0 | 19 | 1200.80 | 0 | 22 | 1413.12 |
Certain device configurations like boot mode and endianess are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.
The logic level present on each device configuration pin is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (for example, FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the SoC. Table 10-29 describes the device configuration pins.
NOTE
If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 4.4.
CONFIGURATION PIN | PIN NO. | IPD/IPU (1) | DESCRIPTION |
---|---|---|---|
LENDIAN(1)(2) | F29 | IPU | Device endian mode (LENDIAN)
|
BOOTMODE[15:0](1)(2) | B30, D29, A35, B29, E29, D30, C30, A30, G30, F31, E30, F30, A31, F24, E24, D24 | IPD | Method of boot
|
AVSIFSEL[1:0](1)(2) | M1, M2 | IPD | AVS interface selection
|
MAINPLLODSEL(1)(2) | E32 | IPD | Main PLL Output divider select
|
ARMAVSSHARED(1) | G24 | IPD | ARM AVS Shared with the rest of SOC AVS
|
BOOTMODE_RSVD(1) | B31 | IPD | Boot mode reserved. Pulldown resistor required on pin. |
DDR3A_MAP_EN(1) | A36 | IPD | Control ARM remapping of DDR3A address space in the lower 4GB (32b space) Mode select
|
Several of the peripherals on the 66AK2Hxx are controlled by the Power Sleep Controller (PSC). By default, the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and deasserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code automatically enables the module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the KeyStone Architecture Power Sleep Controller (PSC) User's Guide.
The 66AK2Hxx device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 10-30.
ADDRESS START | ADDRESS END | SIZE | ACRONYM | DESCRIPTION |
---|---|---|---|---|
0x02620000 | 0x02620007 | 8B | Reserved | |
0x02620008 | 0x02620017 | 16B | Reserved | |
0x02620018 | 0x0262001B | 4B | JTAGID | See Section 10.2.3.3 |
0x0262001C | 0x0262001F | 4B | Reserved | |
0x02620020 | 0x02620023 | 4B | DEVSTAT | See Section 10.2.3.1 |
0x02620024 | 0x02620037 | 20B | Reserved | |
0x02620038 | 0x0262003B | 4B | KICK0 | See Section 10.2.3.4 |
0x0262003C | 0x0262003F | 4B | KICK1 | |
0x02620040 | 0x02620043 | 4B | DSP_BOOT_ADDR0 | The boot address for C66x CorePac0. See Section 10.2.3.5 |
0x02620044 | 0x02620047 | 4B | DSP_BOOT_ADDR1 | The boot address for C66x CorePac1. See Section 10.2.3.5 |
0x02620048 | 0x0262004B | 4B | DSP_BOOT_ADDR2 | The boot address for C66x CorePac2. See Section 10.2.3.5 |
0x0262004C | 0x0262004F | 4B | DSP_BOOT_ADDR3 | The boot address for C66x CorePac3. See Section 10.2.3.5 |
0x02620050 | 0x02620053 | 4B | DSP_BOOT_ADDR4 | The boot address for C66x CorePac4 (66AK2H14/12 only). See Section 10.2.3.5 |
0x02620054 | 0x02620057 | 4B | DSP_BOOT_ADDR5 | The boot address for C66x CorePac5 (66AK2H14/12 only). See Section 10.2.3.5 |
0x02620058 | 0x0262005B | 4B | DSP_BOOT_ADDR6 | The boot address for C66x CorePac6 (66AK2H14/12 only). See Section 10.2.3.5 |
0x0262005C | 0x0262005F | 4B | DSP_BOOT_ADDR7 | The boot address for C66x CorePac7 (66AK2H14/12 only). See Section 10.2.3.5 |
0x02620060 | 0x026200DF | 128B | Reserved | |
0x026200E0 | 0x0262010F | 48B | Reserved | |
0x02620110 | 0x02620117 | 8B | MACID | See Section 11.17 |
0x02620118 | 0x0262012F | 24B | Reserved | |
0x02620130 | 0x02620133 | 4B | LRSTNMIPINSTAT_CLR | See Section 10.2.3.7 |
0x02620134 | 0x02620137 | 4B | RESET_STAT_CLR | See Section 10.2.3.9 |
0x02620138 | 0x0262013B | 4B | Reserved | |
0x0262013C | 0x0262013F | 4B | BOOTCOMPLETE | See Section 10.2.3.10 |
0x02620140 | 0x02620143 | 4B | Reserved | |
0x02620144 | 0x02620147 | 4B | RESET_STAT | See Section 10.2.3.8 |
0x02620148 | 0x0262014B | 4B | LRSTNMIPINSTAT | See Section 10.2.3.6 |
0x0262014C | 0x0262014F | 4B | DEVCFG | See Section 10.2.3.2 |
0x02620150 | 0x02620153 | 4B | PWRSTATECTL | See Section 10.2.3.11 |
0x02620154 | 0x02620157 | 4B | Reserved | |
0x02620158 | 0x0262015B | 4B | Reserved | |
0x0262015C | 0x0262015F | 4B | Reserved | |
0x02620160 | 0x02620160 | 4B | Reserved | |
0x02620164 | 0x02620167 | 4B | Reserved | |
0x02620168 | 0x0262016B | 4B | Reserved | |
0x0262016C | 0x0262017F | 20B | Reserved | |
0x02620180 | 0x02620183 | 4B | SmartReflex Class0 | See Section 11.2.4 |
0x02620184 | 0x0262018F | 12B | Reserved | |
0x02620190 | 0x02620193 | 4B | Reserved | |
0x02620194 | 0x02620197 | 4B | Reserved | |
0x02620198 | 0x0262019B | 4B | Reserved | |
0x0262019C | 0x0262019F | 4B | Reserved | |
0x026201A0 | 0x026201A3 | 4B | Reserved | |
0x026201A4 | 0x026201A7 | 4B | Reserved | |
0x026201A8 | 0x026201AB | 4B | Reserved | |
0x026201AC | 0x026201AF | 4B | Reserved | |
0x026201B0 | 0x026201B3 | 4B | Reserved | |
0x026201B4 | 0x026201B7 | 4B | Reserved | |
0x026201B8 | 0x026201BB | 4B | Reserved | |
0x026201BC | 0x026201BF | 4B | Reserved | |
0x026201C0 | 0x026201C3 | 4B | Reserved | |
0x026201C4 | 0x026201C7 | 4B | Reserved | |
0x026201C8 | 0x026201CB | 4B | Reserved | |
0x026201CC | 0x026201CF | 4B | Reserved | |
0x026201D0 | 0x026201FF | 48B | Reserved | |
0x02620200 | 0x02620203 | 4B | NMIGR0 | See Section 10.2.3.12 |
0x02620204 | 0x02620207 | 4B | NMIGR1 | |
0x02620208 | 0x0262020B | 4B | NMIGR2 | |
0x0262020C | 0x0262020F | 4B | NMIGR3 | |
0x02620210 | 0x02620213 | 4B | NMIGR4 (66AK2H14/12 only) | |
0x02620214 | 0x02620217 | 4B | NMIGR5 (66AK2H14/12 only) | |
0x02620218 | 0x0262021B | 4B | NMIGR6 (66AK2H14/12 only) | |
0x0262021C | 0x0262021F | 4B | NMIGR7 (66AK2H14/12 only) | |
0x02620220 | 0x0262023F | 32B | Reserved | |
0x02620240 | 0x02620243 | 4B | IPCGR0 | See Section 10.2.3.13 |
0x02620244 | 0x02620247 | 4B | IPCGR1 | |
0x02620248 | 0x0262024B | 4B | IPCGR2 | |
0x0262024C | 0x0262024F | 4B | IPCGR3 | |
0x02620250 | 0x02620253 | 4B | IPCGR4 | |
0x02620254 | 0x02620257 | 4B | IPCGR5 | |
0x02620258 | 0x0262025B | 4B | IPCGR6 | |
0x0262025C | 0x0262025F | 4B | IPCGR7 | |
0x02620260 | 0x02620263 | 4B | IPCGR8 | |
0x02620264 | 0x02620267 | 4B | IPCGR9 | |
0x02620268 | 0x0262026B | 4B | IPCGR10 | |
0x0262026C | 0x0262026F | 4B | IPCGR11 | |
0x02620270 | 0x0262027B | 12B | Reserved | |
0x0262027C | 0x0262027F | 4B | IPCGRH | See Section 10.2.3.15 |
0x02620280 | 0x02620283 | 4B | IPCAR0 | See Section 10.2.3.14 |
0x02620284 | 0x02620287 | 4B | IPCAR1 | |
0x02620288 | 0x0262028B | 4B | IPCAR2 | |
0x0262028C | 0x0262028F | 4B | IPCAR3 | |
0x02620290 | 0x02620293 | 4B | IPCAR4 | |
0x02620294 | 0x02620297 | 4B | IPCAR5 | |
0x02620298 | 0x0262029B | 4B | IPCAR6 | |
0x0262029C | 0x0262029F | 4B | IPCAR7 | |
0x026202A0 | 0x026202A3 | 4B | IPCAR8 | |
0x026202A4 | 0x026202A7 | 4B | IPCAR9 | |
0x026202A8 | 0x026202AB | 4B | IPCAR10 | |
0x026202AC | 0x026202AF | 4B | IPCAR11 | |
0x026202B0 | 0x026202BB | 12B | Reserved | |
0x026202BC | 0x026202BF | 4B | IPCARH | See Section 10.2.3.16 |
0x026202C0 | 0x026202FF | 64B | Reserved | |
0x02620300 | 0x02620303 | 4B | TINPSEL | See Section 10.2.3.17 |
0x02620304 | 0x02620307 | 4B | TOUTPSEL | See Section 10.2.3.18 |
0x02620308 | 0x0262030B | 4B | RSTMUX0 | See Section 10.2.3.19 |
0x0262030C | 0x0262030F | 4B | RSTMUX1 | |
0x02620310 | 0x02620313 | 4B | RSTMUX2 | |
0x02620314 | 0x02620317 | 4B | RSTMUX3 | |
0x02620318 | 0x0262031B | 4B | RSTMUX4 | |
0x0262031C | 0x0262031F | 4B | RSTMUX5 | |
0x02620320 | 0x02620323 | 4B | RSTMUX6 | |
0x02620324 | 0x02620327 | 4B | RSTMUX7 | |
0x02620328 | 0x0262032B | 4B | RSTMUX8 | |
0x0262032C | 0x0262032F | 4B | RSTMUX9 | |
0x02620330 | 0x02620333 | 4B | RSTMUX10 | |
0x02620334 | 0x02620337 | 4B | RSTMUX11 | |
0x02620338 | 0x0262034F | 4B | Reserved | |
0x02620350 | 0x02620353 | 4B | MAINPLLCTL0 | See Section 11.5 |
0x02620354 | 0x02620357 | 4B | MAINPLLCTL1 | |
0x02620358 | 0x0262035B | 4B | PASSPLLCTL0 | See Section 11.7 |
0x0262035C | 0x0262035F | 4B | PASSPLLCTL1 | |
0x02620360 | 0x02620363 | 4B | DDR3APLLCTL0 | See Section 11.6 |
0x02620364 | 0x02620367 | 4B | DDR3APLLCTL1 | |
0x02620368 | 0x0262036B | 4B | DDR3BPLLCTL0 | See Section 11.6 |
0x0262036C | 0x0262036F | 4B | DDR3BPLLCTL1 | |
0x02620370 | 0x02620373 | 4B | ARMPLLCTL0 | See Section 10.1.4.1 |
0x02620374 | 0x02620377 | 4B | ARMPLLCTL1 | |
0x02620378 | 0x0262039B | 132B | Reserved | |
0x0262039C | 0x0262039F | 4B | Reserved | |
0x02620400 | 0x02620403 | 4B | ARMENDIAN_CFG0_0 | See Section 10.2.3.21 |
0x02620404 | 0x02620407 | 4B | ARMENDIAN_CFG0_1 | |
0x02620408 | 0x0262040B | 4B | ARMENDIAN_CFG0_2 | |
0x0262040C | 0x026205FF | 62B | Reserved | |
0x02620600 | 0x026206FF | 256B | Reserved | |
0x02620700 | 0x02620703 | 4B | CHIP_MISC_CTL0 | See Section 10.2.3.24 |
0x02620704 | 0x0262070F | 12B | Reserved | |
0x02620710 | 0x02620713 | 4B | SYSENDSTAT | See Section 10.2.3.26 |
0x02620714 | 0x02620717 | 4B | Reserved | |
0x02620718 | 0x0262071B | 4B | Reserved | |
0x0262071C | 0x0262071F | 4B | Reserved | |
0x02620720 | 0x0262072F | 16B | Reserved | |
0x02620730 | 0x02620733 | 4B | SYNECLK_PINCTL | See Section 10.2.3.27 |
0x02620734 | 0x02620737 | 4B | Reserved | |
0x02620738 | 0x0262074F | 24B | USB_PHY_CTL | See Section 10.2.3.28 |
0x02620750 | 0x026207FF | 176B | Reserved | |
0x02620800 | 0x02620C7B | 1148B | Reserved | |
0x02620C7C | 0x02620C7F | 4B | CHIP_MISC_CTL1 | See Section 10.2.3.25 |
0x02620C80 | 0x02620C97 | 24B | Reserved | |
0x02620C90 (silicon revisions 2.0, 3.0, and 3.1) |
0x02620C93 (silicon revisions 2.0, 3.0, and 3.1) |
4B | DEVSPEED | See Section 10.2.3.20 |
0x02620C98 (silicon revision 1.1, 1.0) |
0x02620C9B (silicon revision 1.1, 1.0) |
4B | DEVSPEED | See Section 10.2.3.20 |
0x02620C9C | 0x02620FFF | 868B | Reserved |
The Device Status register depicts device configuration selected upon a power-on reset by the POR or RESETFULL pin. Once set, these bits remain set until a power-on reset. The Device Status register is shown in Figure 10-13 and described in Table 10-31.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | DDR3A_ MAP_EN |
Reserved | ARMAVSSHARED | Rsvd | MAINPLLODSEL | AVSIFSEL | BOOT MODE |
||||||||
R-0000 0000 0000 00 | R-x | R-x | R/W-x | R-x | R/W-x | R/W-xx | R/W-x xxxx xxxx xxxx xxx | ||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOOTMODE | LENDIAN | ||||||||||||||
R/W-x xxxx xxxx xxxx xxx | R-x (1) |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-26 | Reserved | Reserved. Read only, writes have no effect. |
25 | DDR3A_MAP_EN | DDR3A mapping enable
|
24-22 | Reserved | Reserved |
21 | ARMAVSSHARED | ARM AVS Shared with the rest of SOC AVS
|
20 | Reserved | Reserved |
19 | MAINPLLODSEL | Main PLL Output divider select
|
18-17 | AVSIFSEL | AVS interface selection
|
16-1 | BOOTMODE | Determines the boot mode configured for the device. For more information on boot mode, see Section 10.1.2 and the KeyStone Architecture DSP Bootloader User's Guide. |
0 | LENDIAN | Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little endian mode (default).
|
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in Figure 10-14 and described in Table 10-32.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PCIESSMODE | SYSCLK OUTEN |
|||||||||||||||||||||||||||||
R-0 | R/W-00 | R/W-1 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-3 | Reserved | Reserved. Read only, writes have no effect. |
2-1 | PCIESSMODE | Device Type Input of PCIeSS
|
0 | SYSCLKOUTEN | SYSCLKOUT enable
|
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x02620018. The JTAG ID register is shown in Figure 10-15 and described in Table 10-33.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VARIANT | PART NUMBER | MANUFACTURER | LSB | ||||||||||||||||||||||||||||
R-xxxx | R-1011 1001 1000 0001 | R-0000 0010 111 | R-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
31-28 | VARIANT | xxxx | Variant value |
27-12 | PART NUMBER | 1011 1001 1000 0001 | Part Number for boundary scan |
11-1 | MANUFACTURER | 0000 0010 111 | Manufacturer |
0 | LSB | 1 | This bit is read as a 1 |
NOTE
The value of the VARIANT and PART NUMBER fields depends on the silicon revision being used. See the Silicon Errata for details.
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the Bootcfg MMR (memory mapped registers) values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires an MMR write to each of the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is unlocked. See Table 10-30 for the address location. Once released, all the Bootcfg MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is 0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs locks the kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg MMRs, software must always relock the kicker mechanism after completing the MMR writes.
The DSP_BOOT_ADDRn register stores the initial boot fetch address of CorePac_n (n = core number). The fetch address is the public ROM base address (for any boot mode) by default. DSP_BOOT_ADDRn register access should be permitted to any master or emulator when the device is non-secure. CorePac boots from that address when a reset is performed. The DSP_BOOT_ADDRn register is shown in Table 10-1 and described in Table 10-34.
31 | 10 | 9 | 0 | ||||||||||||||||||||||||||||
DSP_BOOT_ADDR | Reserved | ||||||||||||||||||||||||||||||
RW-0010000010110000000000 | R-0 |
Legend: R = Read only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-10 | DSP_BOOT_ADDR | Boot address of CorePac. CorePac boots from that address when a reset is performed. The reset value is 22 MSBs of ROM base address = 0x20B00000. |
9-0 | Reserved | Reserved |
The LRSTNMIPINSTAT register latches the status of LRESET and NMI. The LRESETNMI PIN Status register is shown in Figure 10-16 and described in Table 10-35.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | NMI7 | NMI6 | NMI5 | NMI4 | NMI3 | NMI2 | NMI1 | NMI0 | LR7 | LR6 | LR5 | LR4 | LR3 | LR2 | LR1 | LR0 | |||||||||||||||
R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
Legend: R = Read only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-16 | Reserved | Reserved |
15 | NMI7 | C66x CorePac7 in NMI (66AK2H14/12 only) |
14 | NMI6 | C66x CorePac6 in NMI (66AK2H14/12 only) |
13 | NMI5 | C66x CorePac5 in NMI (66AK2H14/12 only) |
12 | NMI4 | C66x CorePac4 in NMI (66AK2H14/12 only) |
11 | NMI3 | C66x CorePac3 in NMI |
10 | NMI2 | C66x CorePac2 in NMI |
9 | NMI1 | C66x CorePac1 in NMI |
8 | NMI0 | C66x CorePac0 in NMI |
7 | LR7 | C66x CorePac7 in Local Reset (66AK2H14/12 only) |
6 | LR6 | C66x CorePac6 in Local Reset (66AK2H14/12 only) |
5 | LR5 | C66x CorePac5 in Local Reset (66AK2H14/12 only) |
4 | LR4 | C66x CorePac4 in Local Reset (66AK2H14/12 only) |
3 | LR3 | C66x CorePac3 in Local Reset |
2 | LR2 | C66x CorePac2 in Local Reset |
1 | LR1 | C66x CorePac1 in Local Reset |
0 | LR0 | C66x CorePac0 in Local Reset |
The LRSTNMIPINSTAT_CLR register clears the status of LRESET and NMI. The LRESETNMI PIN Status Clear register is shown in Figure 10-17 and described in Table 10-36.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | NMI7 | NMI6 | NMI5 | NMI4 | NMI3 | NMI2 | NMI1 | NMI0 | LR7 | LR6 | LR5 | LR4 | LR3 | LR2 | LR1 | LR0 | |||||||||||||||
R-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 | WC-0 |
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear |
Bit | Field | Description |
---|---|---|
31-16 | Reserved | Reserved |
15 | NMI7 | C66x CorePac7 in NMI Clear (66AK2H14/12 only) |
14 | NM6 | C66x CorePac6 in NMI Clear (66AK2H14/12 only) |
13 | NMI5 | C66x CorePac5 in NMI Clear (66AK2H14/12 only) |
12 | NMI4 | C66x CorePac4 in NMI Clear (66AK2H14/12 only) |
11 | NMI3 | C66x CorePac3 in NMI Clear |
10 | NMI2 | C66x CorePac2 in NMI Clear |
9 | NMI1 | C66x CorePac1 in NMI Clear |
8 | NMI0 | C66x CorePac0 in NMI Clear |
7 | LR7 | C66x CorePac7 in Local Reset Clear (66AK2H14/12 only) |
6 | LR6 | C66x CorePac6 in Local Reset Clear (66AK2H14/12 only) |
5 | LR5 | C66x CorePac5 in Local Reset Clear (66AK2H14/12 only) |
4 | LR4 | C66x CorePac4 in Local Reset Clear (66AK2H14/12 only) |
3 | LR3 | C66x CorePac3 in Local Reset Clear |
2 | LR2 | C66x CorePac2 in Local Reset Clear |
1 | LR1 | C66x CorePac1 in Local Reset Clear |
0 | LR0 | C66x CorePac0 in Local Reset Clear |
The Reset Status register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps.
The Reset Status register is shown in Figure 10-18 and described in Table 10-37.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GR | Reserved | LR7 | LR6 | LR5 | LR4 | LR3 | LR2 | LR1 | LR0 | ||||||||||||||||||||||
R-1 | R-000 0000 0000 0000 0000 0000 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
Legend: R = Read only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31 | GR | Global reset status
|
30-8 | Reserved | Reserved. |
7 | LR7 | C66x CorePac7 reset status (66AK2H14/12 only)
|
6 | LR6 | C66x CorePac6 reset status (66AK2H14/12 only)
|
5 | LR5 | C66x CorePac5 reset status (66AK2H14/12 only)
|
4 | LR4 | C66x CorePac4 reset status (66AK2H14/12 only)
|
3 | LR3 | C66x CorePac3 reset status
|
2 | LR2 | C66x CorePac2 reset status
|
1 | LR1 | C66x CorePac1 reset status
|
0 | LR0 | C66x CorePac0 reset status
|
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear register is shown in Figure 10-19 and described in Table 10-38.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GR | Reserved | LR7 | LR6 | LR5 | LR4 | LR3 | LR2 | LR1 | LR0 | ||||||||||||||||||||||
RW-0 | R-000 0000 0000 0000 0000 0000 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31 | GR | Global reset clear bit
|
30-8 | Reserved | Reserved. |
7 | LR7 | C66x CorePac7 reset clear bit (66AK2H14/12 only)
|
6 | LR6 | C66x CorePac6 reset clear bit (66AK2H14/12 only)
|
5 | LR5 | C66x CorePac5 reset clear bit (66AK2H14/12 only)
|
4 | LR4 | C66x CorePac4 reset clear bit (66AK2H14/12 only)
|
3 | LR3 | C66x CorePac3 reset clear bit
|
2 | LR2 | C66x CorePac2 reset clear bit
|
1 | LR1 | C66x CorePac1 reset clear bit
|
0 | LR0 | C66x CorePac0 reset clear bit
|
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the ROM booting process. The Boot Complete register is shown in Figure 10-20 and described in Table 10-39.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | BC11 | BC10 | BC9 | BC8 | BC7 | BC6 | BC5 | BC4 | BC3 | BC | BC1 | BC0 | |||||||||||||||||||
R,-0000 0000 0000 0000 0000 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-12 | Reserved | Reserved. |
11 | BC11 | ARM CorePac 3 boot status (66AK2H14/12 only)
|
10 | BC10 | ARM CorePac 2 boot status (66AK2H14/12 only)
|
9 | BC9 | ARM CorePac 1 boot status
|
8 | BC8 | ARM CorePac 0 boot status
|
7 | BC7 | C66x CorePac 7 boot status (66AK2H14/12 only)
|
6 | BC6 | C66x CorePac 6 boot status (66AK2H14/12 only)
|
5 | BC5 | C66x CorePac 5 boot status (66AK2H14/12 only)
|
4 | BC4 | C66x CorePac 4 boot status (66AK2H14/12 only)
|
3 | BC3 | C66x CorePac 3 boot status
|
2 | BC2 | C66x CorePac2 boot status
|
1 | BC1 | C66x CorePac1 boot status
|
0 | BC0 | C66x CorePac 0 boot status
|
The BCx bit indicates the boot complete status of the corresponding C66x CorePac. All BCx bits are sticky bits — that is, they can be set only once by the software after device reset and they will be cleared to 0 on all device resets (warm reset and power-on reset).
Boot ROM code is implemented such that each C66x CorePac sets its corresponding BCx bit immediately before branching to the predefined location in memory.
The Power State Control register (PWRSTATECTL) is controlled by the software to indicate the power-saving mode. Under ROM code, the C66x CorePac reads this register to differentiate between the various power saving modes. This register is cleared only by POR and is not changed by any other device reset. See Hardware Design Guide for KeyStone II Devices for more information. The PWRSTATECTL register is shown in Figure 10-21 and described in Table 10-40.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Hibernation Recovery Branch Address | Width | Wait | Recovery Master | Local Reset Action | Stored SR Index | Hibernation Mode | Hibernation | Rsvd | |||||||||||||||||||||||
RW-0000 0000 0000 0000 00 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | R-0 |
Legend: R = Read Only, RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-10 | Hibernation Recovery Branch Address | Used to provide a start address for execution out of the hibernation modes. See the KeyStone Architecture DSP Bootloader User's Guide. |
9 | Width | EMIF16 Width (if the recovery address is in EMIF16 space).
|
8 | Wait | Extended Wait (if the recovery address is in EMIF16 space)
|
7 | Recovery Master | Master performs hibernation recovery
|
6-5 | Local Reset Action | Action of Local Reset
|
4-3 | Stored Index | 0-3 value latched in the SR bits of the DEVSTAT register |
2 | Hibernation Mode | Indicates whether the device is in hibernation mode 1 or mode 2.
|
1 | Hibernation | Indicates whether the device is in hibernation mode or not.
|
0 | Reserved | Reserved |
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The 66AK2Hxx has eight (66AK2H12) or four (66AK2H06) NMIGRx registers (NMIGR0 through NMIGR7). The NMIGR0 register generates an NMI event to C66x CorePac0, the NMIGR1 register generates an NMI event to C66x CorePac1, and so on. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI event generation to the C66x CorePac is shown in Figure 10-22 and described in Table 10-41.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | NMIG | ||||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0000 000 | RW-0 |
Legend: RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-1 | Reserved | Reserved |
0 | NMIG | Reads return 0 Writes:
|
The IPCGRx registers facilitate inter-C66x CorePac interrupts.
The 66AK2H12 device has 12 IPCGRx registers (IPCGR0 through IPCGR11) and the 66AK2H06 has six IPCGRx registers (IPCGR0 through IPCGR3 and IPCGR8 and IPCGR9). These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx register generates an interrupt pulse to the:
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. There can be numerous sources for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation register is shown in Figure 10-23 and described in Table 10-42.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRCS27-SRCS0 | Reserved | IPCG | |||||||||||||||||||||||||||||
RW +0 (per bit field) | R-000 | RW-0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-4 | SRCSx | Reads return current value of internal register bit. Writes:
|
3-1 | Reserved | Reserved |
0 | IPCG | Reads return 0. Writes:
|
The IPCARx registers facilitate inter-CorePac interrupt acknowledgment.
The 66AK2H12 device has 12 IPCARx registers and the 66AK2H06 has six IPCARx registers. These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Acknowledgment register is shown in Figure 10-24 and described in Table 10-43.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRCC27-SRCC0 | Reserved | ||||||||||||||||||||||||||||||
RW +0 (per bit field) | R-0000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-4 | SRCCx | Reads return current value of internal register bit. Writes:
|
3-0 | Reserved | Reserved |
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6) followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight SYSCLK1/6 cycle window — the pulse blocking window. To generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking window has elapsed. The IPC Generation Host register is shown in Figure 10-25 and described in Table 10-44.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRCS27-SRCS0 | Reserved | IPCG | |||||||||||||||||||||||||||||
RW +0 (per bit field) | R-000 | RW +0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-4 | SRCSx | Reads return current value of internal register bit. Writes:
|
3-1 | Reserved | Reserved |
0 | IPCG | Reads return 0. Writes:
|
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the same as for other IPCAR registers. The IPC Acknowledgment Host register is shown in Figure 10-26 and described in Table 10-45.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRCC27-SRCC0 | Reserved | ||||||||||||||||||||||||||||||
RW +0 (per bit field) | R-0000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-4 | SRCCx | Reads the return current value of the internal register bit. Writes:
|
3-0 | Reserved | Reserved |
The Timer Input Selection register selects timer inputs and is shown in Figure 10-27 and described in Table 10-46.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TINPHSEL15 | TINPLSEL15 | TINPHSEL14 | TINPLSEL14 | TINPHSEL13 | TINPLSEL13 | TINPHSEL12 | TINPLSEL12 |
RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TINPHSEL11 | TINPLSEL11 | TINPHSEL10 | TINPLSEL10 | TINPHSEL9 | TINPLSEL9 | TINPHSEL8 | TINPLSEL8 |
RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TINPHSEL7 | TINPLSEL7 | TINPHSEL6 | TINPLSEL6 | TINPHSEL5 | TINPLSEL5 | TINPHSEL4 | TINPLSEL4 |
RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TINPHSEL3 | TINPLSEL3 | TINPHSEL2 | TINPLSEL2 | TINPHSEL1 | TINPLSEL1 | TINPHSEL0 | TINPLSEL0 |
RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
LEGEND: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31 | TINPHSEL15 | Input select for TIMER15 high.
|
30 | TINPLSEL15 | Input select for TIMER15 low.
|
29 | TINPHSEL14 | Input select for TIMER14 high.
|
28 | TINPLSE14 | Input select for TIMER14 low.
|
27 | TINPHSEL13 | Input select for TIMER13 high.
|
26 | TINPLSEL13 | Input select for TIMER13 low.
|
25 | TINPHSEL12 | Input select for TIMER12 high.
|
24 | TINPLSEL12 | Input select for TIMER12low.
|
23 | TINPHSEL11 | Input select for TIMER11 high.
|
22 | TINPLSEL11 | Input select for TIMER11 low.
|
21 | TINPHSEL10 | Input select for TIMER10 high.
|
20 | TINPLSEL10 | Input select for TIMER10 low.
|
19 | TINPHSEL9 | Input select for TIMER9 high.
|
18 | TINPLSEL9 | Input select for TIMER9 low.
|
17 | TINPHSEL8 | Input select for TIMER8 high.
|
16 | TINPLSEL8 | Input select for TIMER8 low.
|
15 | TINPHSEL7 | Input select for TIMER7 high. (66AK2H14/12 only)
|
14 | TINPLSEL7 | Input select for TIMER7 low. (66AK2H14/12 only)
|
13 | TINPHSEL6 | Input select for TIMER6 high. (66AK2H14/12 only)
|
12 | TINPLSEL6 | Input select for TIMER6 low. (66AK2H14/12 only)
|
11 | TINPHSEL5 | Input select for TIMER5 high. (66AK2H14/12 only)
|
10 | TINPLSEL5 | Input select for TIMER5 low. (66AK2H14/12 only)
|
9 | TINPHSEL4 | Input select for TIMER4 high. (66AK2H14/12 only)
|
8 | TINPLSEL4 | Input select for TIMER4 low. (66AK2H14/12 only)
|
7 | TINPHSEL3 | Input select for TIMER3 high.
|
6 | TINPLSEL3 | Input select for TIMER3 low.
|
5 | TINPHSEL2 | Input select for TIMER2 high.
|
4 | TINPLSEL2 | Input select for TIMER2 low.
|
3 | TINPHSEL1 | Input select for TIMER1 high.
|
2 | TINPLSEL1 | Input select for TIMER1 low.
|
The control register TOUTSEL handles the timer output selection and is shown in Figure 10-28 and described in Table 10-47.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | TOUTPSEL1 | TOUTPSEL0 | |||||||||||||||||||||||||||||
R-0000000000000000000000 | RW-00001 | RW-00000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description | |
---|---|---|---|
31-10 | Reserved | Reserved | |
9-5 | TOUTPSEL1 | Output select for TIMO1 | |
|
|
||
4-0 | TOUTPSEL0 | Output select for TIMO0 | |
|
|
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX11 (66AK2H12) or RSTMUX0 through RSTMUX3 (66AK2H06) for each of the C66x CorePacs and RSTMUX8 and RSTMUX9 (66AK2H06) for the ARM CorePac on the device. These registers are in Bootcfg memory space. The Reset Mux register is shown in Figure 10-29 and described in Table 10-48.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0000 0000 0000 0000 0000 00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | EVTSTATCLR | Rsvd | DELAY | EVTSTAT | OMODE | LOCK | |||||||||
R-0000 0000 0000 0000 0000 00 | RC-0 | R-0 | RW-100 | R-0 | RW-000 | RW-0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear |
Bit | Field | Description |
---|---|---|
31-10 | Reserved | Reserved |
9 | EVTSTATCLR | Clear event status
|
8 | Reserved | Reserved |
7-5 | DELAY | Delay cycles between NMI and local reset
|
4 | EVTSTAT | Event status
|
3-1 | OMODE | Timer event operation mode
|
0 | LOCK | Lock register fields
|
The Device Speed register shows the device speed grade and is shown in Figure 10-30 and described in Table 10-49.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | DEVSPEED | Reserved | ARMSPEED | ||||||||||||||||||||||||||||
R-n | R-n | R-n | R-n |
Legend: R = Read only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-28 | Reserved | Reserved. Read only |
27-16 | DEVSPEED | Indicates the speed of the device (read only)
|
15-12 | Reserved | Reserved. Read only |
11-0 | ARMSPEED | Indicates the speed of the ARM (read only)
|
The registers defined in ARM Configuration register 0 (ARMENDIAN_CFGr_0) control the way Cortex-A15 processor core access to peripheral MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is shown in Figure 10-31 and described in Table 10-50.)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASEADDR | Reserved | ||||||||||||||||||||||||||||||
RW-0000 0000 0000 0000 0000 0000 | R-0000 0000 |
Legend: RW = Read/Write; R = Read only |
Bit | Field | Description |
---|---|---|
31-8 | BASEADDR | 24-bit Base Address of Configuration Region R This base address defines the start of a contiguous block of memory-mapped register space for which a word swap is done by the ARM CorePac bridge. |
7-0 | Reserved | Reserved |
The registers defined in ARM Configuration register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is shown in Figure 10-32 and described in Table 10-51.)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SIZE | ||||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0000 | RW-0000 |
Legend: RW = Read/Write; R = Read only |
Bit | Field | Description |
---|---|---|
31-4 | Reserved | Reserved |
3-0 | SIZE | 4-bit encoded size of Configuration Region R The value in the SIZE field defines the size of the contiguous block of memory-mapped register space for which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
|
The registers defined in ARM Configuration register 2 (ARMENDIAN_CFGr_2) enable the word swapping of a region. The ARMENDIAN_CFGr_2 register is shown in Figure 10-33 and described in Table 10-52.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | DIS | ||||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0000 000 | RW-0 |
Legend: RW = Read/Write |
Bit | Field | Description |
---|---|---|
31-1 | Reserved | Reserved |
0 | DIS | Disabling the word swap of a region
|
The Chip Miscellaneous Control (CHIP_MISC_CTL0) register is shown in Figure 10-34 and described in Table 10-53.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | USB_PME_EN | AETMUX SEL1 |
AETMUX SEL0 |
||||||||||||
R-0 | RW-0 | RW-0 | RW-0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Rsvd | MSMC_ BLOCK_ PARITY_ RST |
Reserved | QM_PRIORITY | |||||||||||
RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
Legend: R = Read only; W = Write only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-19 | Reserved | Reserved. |
18 | USB_PME_EN | Enables wakeup event generation from USB
|
17 | AETMUXSEL1 | Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC3 is connected to the C66x Interrupt Controller
|
16 | AETMUXSEL0 | Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC4 is connected to the C66x Interrupt Controller
|
15-14 | Reserved | Reserved |
13 | Reserved | Reserved |
12 | MSMC_BLOCK_PARITY_RST | Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset. |
11-3 | Reserved | Reserved |
2-0 | QM_PRIORITY | Control the priority level for the transactions from QM_Master port, which access the external linking RAM. |
The Chip Miscellaneous Control (CHIP_MISC_CTL1) register is shown in Figure 10-35 and described in Table 10-54.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | IO_TRACE_SEL | ARM_PLL_ EN |
Reserved | ||||||||||||||||||||||||||||
R-0000 0000 00000000 | RW-0 | RW-0 | RW-0000000000000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-15 | Reserved | Reserved. |
14 | IO_TRACE_SEL | This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin
|
13 | ARM_PLL_EN | This bit controls the glitchfree clock mux between bypass clock and ARM PLL output clock
|
12-0 | Reserved |
This register provides a way for reading the system endianness in an endian-neutral way. A zero value indicates big endian and a nonzero value indicates little endian. The SYSENDSTAT register captures the LENDIAN BOOTMODE pin and is used by the BOOTROM to guide the bootflow. The value is latched on the rising edge of POR or RESETFULL . The SYSENDSTAT register is shown in Figure 10-36 and described in Table 10-55.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SYSENDSTAT | ||||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0000 000 | R-0 |
Legend: RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-1 | Reserved | Reserved |
0 | SYSENDSTAT | Reflects the same value as the LENDIAN bit in the DEVSTAT register.
|
This register controls the routing of recovered clock signals from any Ethernet port (SGMII of the multiport switches) to the clock output TSRXCLKOUT0/TSRXCLKOUT1. The SYNECLK_PINCTL register is shown in Figure 10-37 and described in Table 10-56.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | TSRXCLKOUT1SEL | Rsvd | TSRXCLKOUT0SEL | ||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0 | RW-0 | RW-0 |
Legend: RW = Read/Write; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-7 | Reserved | |
6-4 | TSRXCLKOUT1SEL |
|
3 | Reserved | |
2-0 | TSRXCLKOUT0SEL |
|
The USB PHY Control (USB_PHY_CTLx) registers are shown in Figure 10-38, Figure 10-39, Figure 10-40, Figure 10-41, Figure 10-42, and Figure 10-43 and described in Table 10-57, Table 10-58, Table 10-59, Table 10-60, Figure 10-42, and Table 10-62.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PHY_ RTUNE_ ACK |
PHY_ RTUNE_ REQ |
Rsvd | PHY_TC_ VATESTENB |
PHY_TC_TEST_ POWER DOWN_ SSP |
PHY_TC_TEST_ POWER DOWN_ HSP |
PHY_TC_LOOP BACKENB |
Rsvd | UTMI_ VBUS VLDEXT |
UTMI_TXBITSTUFFENH | UTMI_TXBITSTUFFEN | ||||
R-0 | R-0 | R/W-0 | R-0 | R/W-00 | R/W-0 | R/W-0 | R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 |
Legend: R = Read only; W = Write only; -n = value after reset |
Bit | Field | Description |
---|---|---|
31-12 | Reserved | Reserved |
11 | PHY_RTUNE_ACK | The PHY uses an external resistor to calibrate the termination impedances of the PHY's high-speed inputs and outputs. The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each time the PHY is taken out of a reset, a termination calibration is performed. For SS link, the calibration can also be requested externally by asserting the PHY_RTUNE_REQ. When the calibration is complete, the PHY_RTUNE_ACK transitions low. A resistor calibration on the SS link cannot be performed while the link is operational |
10 | PHY_RTUNE_REQ | See PHY_RTUNE_ACK. |
9 | Reserved | Reserved |
8-7 | PHY_TC_VATESTENB | Analog Test Pin Select. Enables analog test voltages to be placed on the ID pin.
|
6 | PHY_TC_TEST_POWERDOWN_SSP | SS Function Circuits Power-Down Control. Powers down all SS function circuitry in the PHY for IDDQ testing. |
5 | PHY_TC_TEST_POWERDOWN_HSP | HS Function Circuits Power-Down Control Powers down all HS function circuitry in the PHY for IDDQ testing. |
4 | PHY_TC_LOOPBACKENB | Loop-back Test Enable Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive and transmit logic.
|
3 | Reserved |
|
2 | UTMI_VBUSVLDEXT | External VBUS Valid Indicator Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1. VBUSVLDEXT indicates whether the VBUS signal on the USB cable is valid. In addition, VBUSVLDEXT enables the pull-up resistor on the D+ line.
|
1 | UTMI_TXBITSTUFFENH | High-byte Transmit Bit-Stuffing Enable Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.
|
0 | UTMI_TXBITSTUFFEN | Low-byte Transmit Bit-Stuffing Enable Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.
|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PIPE_REF_CLKREQ_N | PIPE_TX2RX_LOOPBK | PIPE_EXT_PCLK_ REQ |
PIPE_ALT_CLK_ SEL |
PIPE_ALT_CLK_ REQ |
PIPE_ALT_CLK_EN | |||||||||
R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R-0 | R/W-0 |
Legend: R = Read only; R/W = Read/Write, -n = value after reset |
Bit | Field | Description |
---|---|---|
31-6 | Reserved | Reserved |
5 | PIPE_REF_CLKREQ_N | Reference Clock Removal Acknowledge. When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state, PIPE_REF_CLKREQ_N is asserted after the PLL is stable and the reference clock can be removed. |
4 | PIPE_TX2RX_LOOPBK | Loop-back. When this signal is asserted, data from the transmit predriver is looped back to the receiver slicers. LOS is bypassed and based on the tx_en input so that rx_los=!tx_data_en. |
3 | PIPE_EXT_PCLK_REQ | External PIPE Clock Enable Request. When asserted, this signal enables the pipeP_pclk output regardless of power state (along with the associated increase in power consumption). |
2 | PIPE_ALT_CLK_SEL | Alternate Clock Source Select. Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.
Change only during a reset. |
1 | PIPE_ALT_CLK_REQ | Alternate Clock Source Request. Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master MPLL). Connect to the alt_clk_en on the master. |
0 | PIPE_ALT_CLK_EN | Alternate Clock Enable. Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL). |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | PHY_PC_LOS_BIAS | PHY_PC_TXVREFTUNE | PHY_PC_ TXRISETUNE |
PHY_PC_ TXRESTUNE |
PHY_PC_ TX PREEMP PULSE T UNE |
PHY_PC_TXPREEMPAMPTUNE | |||||||||
R-0 | R/W-101 | R/W-1000 | R/W-01 | R/W-01 | R/W-0 | R/W-00 | |||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_PC_ TXHSXVTUNE |
PHY_PC_TXFSLSTUNE | PHY_PC_SQRXTUNE | PHY_PC_OTGTUNE | Rsvd | PHY_PC_ COMPDISTUNE |
||||||||||
R/W-11 | R/W-0011 | R/W-011 | R/W-100 | R-0 | R/W-100 |
Legend: R = Read only; R/W = Read/Write, -n = value after reset |
Bit | Field | Description |
---|---|---|
31-30 | Reserved | Reserved |
29-27 | PHY_PC_LOS_BIAS | Loss-of-Signal Detector Threshold Level Control. Sets the LOS detection threshold level.
Note: the 000b setting is reserved and must not be used. |
26-23 | PHY_PC_TXVREFTUNE | HS DC Voltage Level Adjustment. Adjusts the high-speed DC level voltage.
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22-21 | PHY_PC_TXRISETUNE | HS Transmitter Rise/Fall TIme Adjustment. Adjusts the rise/fall times of the high-speed waveform.
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20-19 | PHY_PC_TXRESTUNE | USB Source Impedance Adjustment. Some applications require additional devices to be added on the USB, such as a series switch, which can add significant series resistance. This bus adjusts the driver source impedance to compensate for added series resistance on the USB. |
18 | PHY_PC_ TXPREEMPPULSETUNE |
HS Transmitter Pre-Emphasis Duration Control. Controls the duration for which the HS pre-emphasis current is sourced onto DP or DM. It is defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and is defined as 1x pre-emphasis duration. This signal valid only if either txpreempamptune[1] or txpreempamptune[0] is set to 1.
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17-16 | PHY_PC_TXPREEMPAMPTUNE | HS Transmitter Pre-Emphasis Current Control. Controls the amount of current sourced to DP and DM after a J-to-K or K-to-J transition. The HS Transmitter pre-emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 µA and is defined as 1x pre-emphasis current.
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15-14 | PHY_PC_TXHSXVTUNE | Transmitter High-Speed Crossover Adjustment. Adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode.
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13-10 | PHY_PC_TXFSLSTUNE | FS/LS Source Impedance Adjustment. Adjusts the low- and full-speed single-ended source impedance while driving high. This parameter control is encoded in thermometer code.
Any nonthermometer code setting (that is 1001) is not supported and reserved. |
9-7 | PHY_PC_SQRXTUNE | Squelch Threshold Adjustment. Adjusts the voltage level for the threshold used to detect valid high-speed data.
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6-4 | PHY_PC_OTGTUNE | VBUS Valid Threshold Adjustment. Adjusts the voltage level for the VBUS valid threshold.
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3 | Reserved | Reserved |
2-0 | PHY_PC_COMPDISTUNE | Disconnect Threshold Adjustment. Adjusts the voltage level for the threshold used to detect a disconnect event at the host.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | PHY_PC_PCS_TX_SWING_FULL | PHY_PC_PCS_TX_DEEMPH_6DB | Rsvd | ||||||||||||
R-0 | R/W-1111000 | R/W-100000 | R-0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PHY_PC_PCS_TX_DEEMPH_3P5DB | PHY_PC_LOS_LEVEL | |||||||||||||
R-0 | R/W-010101 | R/W-01001 |
Legend: R = Read only; R/W = Read/Write, -n = value after reset |
Bit | Field | Description |
---|---|---|
31-30 | Reserved | Reserved |
29-23 | PHY_PC_PCS_TX_SWING_ FULL |
Tx Amplitude (Full Swing Mode). Sets the launch amplitude of the transmitter. It can be used to tune Rx eye for compliance. |
22-17 | PHY_PC_PCS_TX_DEEMPH_ 6DB |
Tx De-Emphasis at 6 dB. Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch amplitude. |
16-11 | Reserved | Reserved |
10-5 | PHY_PC_PCS_TX_DEEMPH_ 3P5DB |
Tx De-Emphasis at 3.5 dB. Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to the PIPE3 specification). Can be used for Rx eye compliance. |
4-0 | PHY_PC_LOS_LEVEL | Loss-of-Signal Detector Sensitivity Level Control. Sets the LOS detection threshold level. This signal must be set to 0x9. |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PHY_SSC_EN | PHY_REF_USE_ PAD |
PHY_REF_SSP_EN | PHY_ MPLL_ REFSSC_ CLK_EN |
PHY_FSEL | PHY_RETENABLEN | PHY_REFCLKSEL | PHY_ COMMON ONN |
Rsvd | PHY_OTG_VBUSVLDEXTSEL | ||||||
R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-100111 | R/W-1 | R/W-10 | R/W-0 | R-0 | R/W-0 | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_OTG _ OTG DISABLE |
PHY_PC_TX_VBOOST_LVL | PHY_PC_LANE0_TX_TERM_ OFFSET |
Reserved | ||||||||||||
R/W-1 | R/W-100 | R/W-00000 | R-0 |
Legend: R = Read only; R/W = Read/Write, -n = value after reset |
Bit | Field | Description |
---|---|---|
31 | PHY_SSC_EN | Spread Spectrum Enable. Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0 PHY. If the reference clock already has spread spectrum applied, ssc_en must be deasserted. |
30 | PHY_REF_USE_PAD | Select Reference Clock Connected to ref_pad_clk_{p,m}. When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source. When deasserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source. |
29 | PHY_REF_SSP_EN | Reference Clock Enables for SS function. Enables the reference clock to the prescaler. The ref_ssp_en signal must remain deasserted until the reference clock is running at the appropriate frequency, at which point ref_ssp_en can be asserted. For lower power states, ref_ssp_en can also be de asserted. |
28 | PHY_MPLL_REFSSC_CLK_EN | Double-Word Clock Enable. Enables/disables the mpll_refssc_clk signal. To prevent clock glitch, it must be changed when the PHY is inactive. |
27-22 | PHY_FSEL | Frequency Selection. Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals will determine the clock frequency used for SS and HS operations and if a shared or separate reference clock will be used. |
21 | PHY_RETENABLEN | Lowered Digital Supply Indicator. Indicates that the vp digital power supply has been lowered in Suspend mode. This signal must be deasserted before the digital power supply is lowered.
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20-19 | PHY_REFCLKSEL | Reference Clock Select for PLL Block. Selects reference clock source for the HS PLL block.
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18 | PHY_COMMONONN | Common Block Power-Down Control. Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in Suspend or Sleep mode.
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17 | Reserved | Reserved |
16 | PHY_OTG_VBUSVLDEXTSEL | External VBUS Valid Select. Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the VBUS signal on the USB cable is valid.
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15 | PHY_OTG_OTGDISABLE | OTG Block Disable. Powers down the OTG block, which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP in Device mode) is always on irrespective of the state of otgdisable. If the application does not use the OTG function, setting this signal to high to save power.
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14-12 | PHY_PC_TX_VBOOST_LVL | Tx Voltage Boost Level. Sets the boosted transmit launch amplitude (mVppd). The default setting is intended to set the launch amplitude to approximately 1,008mVppd.
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11-7 | PHY_PC_LANE0_TX_TERM_ OFFSET |
Transmitter Termination Offset. Enables adjusting the transmitter termination value from the default value of 60 Ω. |
6-0 | Reserved | Reserved |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | PHY_REF_CLKDIV2 | PHY_MPLL_MULTIPLIER[6:0] | |||||||||||||
R-0 | R/W-0 | R/W +0011001 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_MPLL_MULTIPLIER[6:0] | PHY_SSC_REF_CLK_SEL | Rsvd | PHY_SSC_RANGE | ||||||||||||
R/W +0011001 | R/W-000000000 | R-0 | R/W-000 |
Legend: R = Read only; R/W = Read/Write, -n = value after reset |
Bit | Field | Description |
---|---|---|
31-21 | Reserved | Reserved |
20 | PHY_REF_CLKDIV2 | Input Reference Clock Divider Control. If the input reference clock frequency is greater than 100 MHz, this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL. When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference clock frequency divided by 4. |
19-13 | PHY_MPLL_MULTIPLIER[6:0] | MPLL Frequency Multiplier Control. Multiplies the reference clock to a frequency suitable for intended operating speed. |
12-4 | PHY_SSC_REF_CLK_SEL | Spread Spectrum Reference Clock Shifting. Enables nonstandard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient.
|
3 | Reserved | Reserved |
2-0 | PHY_SSC_RANGE | Spread Spectrum Clock Range. Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator. |