SNAS305J July   2005  – March 2016 ADC121S021

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Shutdown Mode
  10. 10Applications Information
    1. 10.1 Application Information
      1. 10.1.1 Using the ADC121S021
        1. 10.1.1.1 Determining Throughput
      2. 10.1.2 ADC121S021 Transfer Function
      3. 10.1.3 Analog Inputs
      4. 10.1.4 Digital Inputs And Outputs
      5. 10.1.5 Power Management
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Noise Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

13 Device and Documentation Support

13.1 Device Support

13.1.1 Device Nomenclature

    ACQUISITION TIME The time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS when the signal is sampled and the part moves from track to hold. The start of the time interval that contains tACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold to track. The user must ensure that the time between the 13th rising edge of SCLK and the falling edge of the next CS is not less than tACQ to meet performance specifications.
    APERTURE DELAY The time after the falling edge of CS to when the input signal is acquired or held for conversion.
    APERTURE JITTER (APERTURE UNCERTAINTY) The variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output.
    CONVERSION TIME The time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th falling edge of SCLK when the SDATA output goes into TRI-STATE.
    DIFFERENTIAL NON-LINEARITY (DNL) The measure of the maximum deviation from the ideal step size of 1 LSB.
    DUTY CYCLE The ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK.
    EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) Another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
    FULL POWER BANDWIDTH A measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.
    GAIN ERROR The deviation of the last code transition (111...110) to (111...111) from the ideal (VREF – 1.5 LSB), after adjusting for offset error.
    INTEGRAL NON-LINEARITY (INL) A measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value.
    INTERMODULATION DISTORTION (IMD) The creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB.
    MISSING CODES Output codes that never appears at the ADC outputs. The ADC121S021 is ensured not to have any missing codes.
    OFFSET ERROR The deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).
    SIGNAL TO NOISE RATIO (SNR) The ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC
    SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) The ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC
    SPURIOUS FREE DYNAMIC RANGE (SFDR) The difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
    TOTAL HARMONIC DISTORTION (THD) The ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as:
    Equation 5. ADC121S021 20145199.gif

    where

    • Af1 is the RMS power of the input frequency at the output
    • Af2 through Af6 are the RMS power in the first 5 harmonic frequencies
    THROUGHPUT TIME The minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time.

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.3 Trademarks

SPI, QSPI, E2E are trademarks of Texas Instruments.

TRI-STATE is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.