SNAS305J July   2005  – March 2016 ADC121S021

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Shutdown Mode
  10. 10Applications Information
    1. 10.1 Application Information
      1. 10.1.1 Using the ADC121S021
        1. 10.1.1.1 Determining Throughput
      2. 10.1.2 ADC121S021 Transfer Function
      3. 10.1.3 Analog Inputs
      4. 10.1.4 Digital Inputs And Outputs
      5. 10.1.5 Power Management
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Noise Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DBV Package
6-Pin SOT-23
Top View
See package number DBV0006A.
NGF Package
6-Pin WSON
Top View
See package number NGF0006A.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
CS 6 Digital I/O Chip select. On the falling edge of CS, a conversion process begins.
GND 2 PWR The ground return for the supply and signals.
SCLK 4 Digital I/O Digital clock input. This clock directly controls the conversion and readout processes.
SDATA 5 Digital I/O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
VA 1 PWR Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin.
VIN 3 Analog I/O Analog input. This signal can range from 0 V to VA.
PAD — PWR For package suffix CISD(X) only, TI recommends connecting the center pad to ground.