7.3.1 Operation

Simplified schematics of the ADC128S052 in both track and hold operation are shown in Figure 34 and Figure 35, respectively. In Figure 34, the ADC128S052 is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC128S052 is in this state for the first three SCLK cycles after CS is brought low.

Figure 35 shows the ADC128S052 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC128S052 is in this state for the last thirteen SCLK cycles after CS is brought low.

Figure 34. ADC128S052 in Track Mode

Figure 35. ADC128S052 in Hold Mode

7.3.2 Transfer Function

The output format of the ADC128S052 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC128S052 is V_A / 4096. The ideal transfer characteristic is shown in Figure 36. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of V_A / 8192. Other code transitions occur at steps of one LSB.

Figure 36. Ideal Transfer Characteristic

7.5.1 Serial Interface

Figure 1 shows a operational timing diagram, and Figure 2 shows a serial interface timing diagram for the ADC128S052. CS (chip select) initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the control register of the device is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS is brought high.

During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished, and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC re-enters the track mode on the falling edge of SCLK after the N × 16th rising edge of SCLK and re-enter the hold/convert mode on the N × 16 + 4th falling edge of SCLK. N is an integer value.

The ADC128S052 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high, and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously, and the ADC enters track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.

While a conversion is in progress, the address of the next input for conversion is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, Table 3.

There is no need to incorporate a power-up delay or dummy conversion as the ADC128S052 is able to acquire the input signal to full resolution in the first conversion immediately following power up. The first conversion result after power-up is that of IN0.

Table 1. Control Register Bits

Table 2. Control Register Bit Descriptions

Table 3. Input Channel Selection