デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The ADC128S102 device is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of 50 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. The device can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC128S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from 2.7 V to 5.25 V, and the digital supply (VD) can range from 2.7 V to VA. Normal power consumption using a 3-V or 5-V supply is 2.3 mW and 10.7 mW, respectively. The power-down feature reduces the power consumption to 0.06 µW using a 3-V supply and 0.25 µW using a 5-V supply.
Changes from O Revision (November 2016) to P Revision
Changes from N Revision (September 2015) to O Revision
Changes from H Revision (October 2009) to N Revision
Changes from G Revision (October 2009) to H Revision
Changes from F Revision (June 2009) to G Revision
Changes from E Revision (April 2009) to F Revision
Changes from D Revision (January 2009) to E Revision
Changes from C Revision (November 2008) to D Revision
Changes from B Revision (August 2008) to C Revision
Changes from A Revision (August 2008) to B Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
VA | Analog supply voltage | –0.3 | 6.5 | V |
VD | Digital supply voltage(4) | –0.3 | VA + 0.3 | V |
Voltage on any pin to GND | –0.3 | VA + 0.3 | V | |
Input current at any pin (2) | ±10 | mA | ||
Power dissipation TA = 25°C | See (3) | |||
Package input current(2) | ±20 mA | mA | ||
Soldering temperature, 10 seconds | 260 | °C | ||
Junction temperature | 175 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±8000 | V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Operating temperature | –55 | 125 | °C | |
VA supply voltage | 2.7 | 5.25 | V | |
VD supply voltage | 2.7 | VA | V | |
Digital input voltage | 0 | VA | V | |
Analog input voltage | 0 | VA | V | |
Clock frequency | 0.8 | 16 | MHz |
THERMAL METRIC(1) | ACD128S102QML-SP | UNIT | |
---|---|---|---|
NAC (CFP) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 127 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 11.2 | °C/W |
PARAMETER | TEST CONDITIONS | SUBGROUP | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
STATIC CONVERTER CHARACTERISTICS | ||||||||
Resolution with no missing codes | 12 | Bits | ||||||
INL | Integral non-linearity (end point method) | VA = VD = 3 V | [1, 2, 3] | –1 | ±0.6 | 1.1 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.25 | ±0.9 | 1.4 | LSB | |||
DNL | Differential non-linearity | VA = VD = 3 V | [1, 2, 3] | 0.5 | 0.9 | LSB | ||
[1, 2, 3] | –0.7 | –0.3 | LSB | |||||
VA = VD = 5 V | [1, 2, 3] | 0.9 | 1.5 | LSB | ||||
[1, 2, 3] | –0.9 | −0.5 | LSB | |||||
VOFF | Offset error | VA = VD = 3 V | [1, 2, 3] | –2.3 | 0.8 | 2.3 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –2.3 | 1.1 | 2.3 | LSB | |||
OEM | Offset error match | VA = VD = 3 V | [1, 2, 3] | –1.5 | ±0.1 | 1.5 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.5 | ±0.3 | 1.5 | LSB | |||
FSE | Full scale error | VA = VD = 3 V | [1, 2, 3] | –2 | 0.8 | 2 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –2 | 0.3 | 2 | LSB | |||
FSEM | Full scale error match | VA = VD = 3 V | [1, 2, 3] | –1.5 | ±0.1 | 1.5 | LSB | |
VA = VD = 5 V | [1, 2, 3] | –1.5 | ±0.3 | 1.5 | LSB | |||
DYNAMIC CONVERTER CHARACTERISTICS | ||||||||
FPBW | Full power bandwidth (–3 dB) | VA = VD = 3 V | 6.8 | MHz | ||||
VA = VD = 5 V | 10 | MHz | ||||||
SINAD | Signal-to-noise plus distortion ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68 | 72 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68 | 72 | dB | ||||
SNR | Signal-to-noise ratio | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 69 | 72 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 68.5 | 72 | dB | ||||
THD | Total harmonic distortion | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | –86 | –74 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | –87 | –74 | dB | ||||
SFDR | Spurious-free dynamic range | VA = VD = 3 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 75 | 91 | dB | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 75 | 90 | dB | ||||
ENOB | Effective number of bits | VA = VD = 3 V, fIN = 40.2 kHz |
[4, 5, 6] | 11.1 | 11.6 | Bits | ||
VA = VD = 5 V, fIN = 40.2 kHz, −0.02 dBFS |
[4, 5, 6] | 11.1 | 11.6 | Bits | ||||
ISO | Channel-to-channel isolation | VA = VD = 3 V, fIN = 20 kHz |
84 | dB | ||||
VA = VD = 5 V, fIN = 20 kHz, −0.02 dBFS |
85 | dB | ||||||
IMD | Intermodulation distortion, second order terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –93 | –78 | dB | ||
VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –93 | –78 | dB | ||||
Intermodulation distortion, third order terms | VA = VD = 3 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –91 | –70 | dB | |||
VA = VD = 5 V, fa = 19.5 kHz, fb = 20.5 kHz |
[4, 5, 6] | –91 | –70 | dB | ||||
ANALOG INPUT CHARACTERISTICS | ||||||||
VIN | Input range | 0 to VA | V | |||||
IDCL | DC leakage current | [1, 2, 3] | ±0.01 | ±1 | µA | |||
CINA | Input capacitance | Track mode, see (2) | 38 | pF | ||||
Hold mode, see (2) | 4.5 | pF | ||||||
DIGITAL INPUT CHARACTERISTICS | ||||||||
VIH | Input high voltage | VA = VD = 2.7 V to 3.6 V | [1, 2, 3] | 2.1 | V | |||
VA = VD = 4.75 V to 5.25 V | [1, 2, 3] | 2.4 | V | |||||
VIL | Input low voltage | VA = VD = 2.7 V to 5.25 V | [1, 2, 3] | 0.8 | V | |||
IIN | Input current | VIN = 0 V or VD | [1, 2, 3] | ±1 | ±1 | µA | ||
CIND | Digital input capacitance | See (2) | 3.5 | pF | ||||
DIGITAL OUTPUT CHARACTERISTICS | ||||||||
VOH | Output high voltage | ISOURCE = 200 µA, VA = VD = 2.7 V to 5.25 V |
[1, 2, 3] | VD –0.5 | V | |||
VOL | Output low voltage | ISINK = 200 µA to 1 mA, VA = VD = 2.7 V to 5.25 V |
[1, 2, 3] | 0.4 | V | |||
IOZH, IOZL | Hi-impedance output leakage current | VA = VD = 2.7 V to 5.25 V | [1, 2, 3] | ±0.01 | ±1 | µA | ||
COUT | Hi-impedance output capacitance | See (2) | 3.5 | pF | ||||
Output coding | Straight (Natural) Binary | |||||||
POWER SUPPLY CHARACTERISTICS (CL = 10 pF) | ||||||||
VA, VD | Analog and digital supply voltages | VA ≥ VD | [1, 2, 3] | 2.7 | V | |||
[1, 2, 3] | 5.25 | V | ||||||
IA + ID | Total supply current, normal mode ( CS low) |
VA = VD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 0.9 | 1.5 | mA | ||
VA = VD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 2.2 | 3.1 | mA | ||||
Total supply current, shutdown mode (CS high) |
VA = VD = 2.7 V to 3.6 V, fSCLK = 0 kSPS |
[1, 2, 3] | 0.11 | 1 | μA | |||
VA = VD = 4.75 V to 5.25 V, fSCLK = 0 kSPS |
[1, 2, 3] | 0.12 | 1.4 | μA | ||||
PC | Power consumption, normal mode ( CS low) |
VA = VD = 3 V fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 2.7 | 4.5 | mW | ||
VA = VD = 5 V fSAMPLE = 1 MSPS, fIN = 40 kHz |
[1, 2, 3] | 11.0 | 15.5 | mW | ||||
Power consumption, shutdown mode (CS high) |
VA = VD = 3 V fSCLK = 0 kSPS |
[1, 2, 3] | 0.33 | 3 | µW | |||
VA = VD = 5 V fSCLK = 0 kSPS |
[1, 2, 3] | 0.6 | 7 | µW | ||||
AC ELECTRICAL CHARACTERISTICS | ||||||||
fSCLKMIN | Minimum clock frequency | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 0.8 | MHz | |||
fSCLK | Maximum clock frequency | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 16 | MHz | |||
fS | Sample rate continuous mode | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 50 | kSPS | |||
[9, 10, 11] | 1 | MSPS | ||||||
tCONVERT | Conversion (hold) time | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 13 | SCLK cycles | |||
DC | SCLK duty cycle | VA = VD = 2.7 V to 5.25 V | MIN | 40% | ||||
MAX | 60% | |||||||
tACQ | Acquisition (track) time | VA = VD = 2.7 V to 5.25 V | [9, 10, 11] | 3 | SCLK cycles | |||
Throughput time | Acquisition time + conversion time VA = VD = 2.7 V to 5.25 V |
[9, 10, 11] | 16 | SCLK cycles | ||||
tAD | Aperture delay | VA = VD = 2.7 V to 5.25 V | 4 | ns |
PARAMETER | TEST CONDITIONS | SUBGROUP | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
IA + ID | Total supply current shutdown mode (CS high) | VA = VD = 2.7 V to 3.6 V, fSCLK = 0 kSPS |
[1] | 30 | µA | ||
VA = VD = 4.75 V to 5.25 V, fSCLK = 0 kSPS |
[1] | 100 | µA | ||||
IOZH, IOZL | Hi-impedance output leakage current | VA = VD = 2.7 V to 5.25 V | [1] | ±10 | µA |
SUBGROUP | MIN | NOM(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
tCSH | CS hold time after SCLK rising edge | See (2) | [9, 10, 11] | 10 | 0 | ns | |
tCSS | CS setup time prior to SCLK rising edge | See (2) | [9, 10, 11] | 10 | 4.5 | ns | |
tEN | CS falling edge to DOUT enabled | [9, 10, 11] | 5 | 30 | ns | ||
tDACC | DOUT access time after SCLK falling edge | [9, 10, 11] | 17 | 27 | ns | ||
tDHLD | DOUT hold time after SCLK falling edge | [9, 10, 11] | 7 | ns | |||
tDS | DIN setup time prior to SCLK rising edge | [9, 10, 11] | 10 | ns | |||
tDH | DIN hold time after SCLK rising edge | [9, 10, 11] | 10 | ns | |||
tCH | SCLK high time | 0.4 × tSCLK | ns | ||||
tCL | SCLK low time | 0.4 × tSCLK | ns | ||||
tDIS | CS rising edge to DOUT high-impedance | DOUT falling | [9, 10, 11] | 2.4 | 20 | ns | |
DOUT rising | [9, 10, 11] | 0.9 | 20 | ns |
SUBGROUP | DESCRIPTION | TEMP (°C) |
---|---|---|
1 | Static tests at | 25 |
2 | Static tests at | 125 |
3 | Static tests at | –55 |
4 | Dynamic tests at | 25 |
5 | Dynamic tests at | 125 |
6 | Dynamic tests at | –55 |
7 | Functional tests at | 25 |
8A | Functional tests at | 125 |
8B | Functional tests at | –55 |
9 | Switching tests at | 25 |
10 | Switching tests at | 125 |
11 | Switching tests at | –55 |
12 | Setting time at | 25 |
13 | Setting time at | 125 |
14 | Setting time at | –55 |
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a charge redistribution digital-to-analog converter.
The output format of the ADC128S102 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC128S102 is VA / 4096. The ideal transfer characteristic is shown in Figure 34. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA / 8192. Other code transitions occur at steps of one LSB.
An equivalent circuit for one of the input channels of the ADC128S102 is shown in Figure 35. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 35 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the ON-resistance of the multiplexer and track or hold switch and is typically 500 Ω. Capacitor C2 is the ADC128S102 sampling capacitor, and is typically 30 pF. The ADC128S102 will deliver best performance when driven by a low-impedance source (less than 100 Ω). This is especially important when using the ADC128S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing filters.
The digital inputs of the ADC128S102 (SCLK, CS, and DIN) have an operating range of 0 V to VA. The inputs are not prone to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT) operating range is controlled by VD. The output high voltage is VD – 0.5 V (minimum) while the output low voltage is 0.4 V (maximum).
Careful consideration should be given to environmental conditions when using a product in a radiation environment.
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level listed in the Device Information table in the Description section. Testing and qualification of these products is done on a wafer level according to MIL-STD-883G, Test Method 1019.7. Testing is done according to Condition A and the Extended room temperature anneal test described in section 3.11 for application environment dose rates less than 0.027 rad(Si)/s. Wafer level TID data is available with lot shipments.
One-time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in Features is the maximum LET tested. A test report is available upon request.
A report on single event upset (SEU) is available upon request.
Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 36 and Figure 37 respectively. In Figure 36, the ADC128S102 is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC128S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 37 shows the ADC128S102 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC128S102 is in this state for the last thirteen SCLK cycles after CS is brought low.
An operational timing diagram and a serial interface timing diagram for the ADC128S102 are shown in Figure 1 to Figure 3. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S102's Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high and is active when CS is low. Note that CS is asynchronous. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS is brought high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N×16+4th falling edge of SCLK. "N" is an integer value.
The ADC128S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters track mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 3 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. The control register is loaded with data indicating the input channel to be converted on the subsequent conversion (see Table 2, Table 3, and Table 4).
Although the ADC128S102 is able to acquire the input signal to full resolution in the first conversion immediately following power-up, the first conversion result after power-up will be that of a randomly selected channel. Therefore, the user needs to incorporate a dummy conversion to set the required channel that will be used on the subsequent conversion.
BIT 7 (MSB) | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
DONTC | DONTC | ADD2 | ADD1 | ADD0 | DONTC | DONTC | DONTC |
BIT | SYMBOL | DESCRIPTION |
---|---|---|
7, 6, 2, 1, 0 | DONTC | Don't care. The values of these bits do not affect the device. |
5 | ADD2 | These three bits determine which input channel will be sampled and converted at the next conversion cycle. The mapping between codes and channels is shown in Table 4. |
4 | ADD1 | |
3 | ADD0 |
ADD2 | ADD1 | ADD0 | INPUT CHANNEL |
---|---|---|---|
0 | 0 | 0 | IN0 |
0 | 0 | 1 | IN1 |
0 | 1 | 0 | IN2 |
0 | 1 | 1 | IN3 |
1 | 0 | 0 | IN4 |
1 | 0 | 1 | IN5 |
1 | 1 | 0 | IN6 |
1 | 1 | 1 | IN7 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ADC128S102 device is a low-power, eight-channel 12-bit ADC with ensured performance specifications from 50 kSPS to 1 MSPS. It is appropriate to utilize the ADC128S102 at sample rates below 50 kSPS by powering the device down (de-asserting CSB) in between conversions. The Electrical Characteristics information highlights the clock frequency where the ADC’s performance is ensured. There is no limitation on periods of time for shutdown between conversions.
A typical application is shown in Figure 38. The split analog and digital supply pins are both powered in this example by the Texas Instruments LP2950-N low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC128S102. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors. The ADC128S102 uses the analog supply (VA) as its reference voltage, so it is very important that VA be kept as clean as possible. Due to the low power requirements of the ADC128S102, it is also possible to use a precision reference as a power supply.
A positive supply only data acquisition system capable of digitizing up to eight single-ended input signals ranging from 0 to 5 V with BW = 10 kHz and a throughput up to 500 kSPS. The ADC128S102 has to interface to an MCU whose supply is set at 5 V. If it is necessary to interface with an MCU that operates at 3.3 V or lower, VA and VD will need to be separated and care must be taken to ensure that VA is powered before VD.
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from the fact that VA is also a reference potential for the ADC. If the requirement of interfacing to the MCU changes to 3.3-V, it will be necessary to change the VD supply voltage to 3.3 V. The maximum sampling rate of the ADC128S102 when all channels (eight) are enabled is, Fs = FSCLK / (16 × 8).
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be sampled at the maximum rate of Fs (single) = FSCLK / 16.
The VA and VD pins are separated by a 51-Ω resistor in order to minimize digital noise from corrupting the analog reference input. If additional filtering is required, the resistor can be replaced by a ferrite bead, thus achieving a 2nd-order filter response. Further noise consideration could be given to the SPI interface, especially when the master MCU is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal path may help in reducing the ground bounce, and thus improve the overall noise performance of the system. Care should be taken when the signal source is capable of producing voltages beyond VA. In such instances, the internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action use Schottky diodes.
There are three major power supply concerns with this product: power supply sequencing, power management, and the effect of digital supply noise on the analog supply.
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, during a conversion cycle. Therefore, VA must ramp up before or concurrently with VD.
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent conversion (see Figure 1).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical specifications. The Power Consumption versus SCLK curve in the Typical Characteristics shows the typical power consumption of the ADC128S102. To calculate the power consumption (PC), simply multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1.
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly into the analog supply, causing greater performance degradation than would noise on the digital supply alone. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. Because the series resistor and the load capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC128S102 due to supply noise, do not use the same supply for the ADC128S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (for example, a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so forth) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the analog ground plane at a single, quiet point.
For related documentation, see the following:
where
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
MICROWIRE, E2E are trademarks of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc..
All other trademarks are the property of their respective owners.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.