SNAS519H July   2011  – August 2015 ADC12D1000RF , ADC12D1600RF

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Static Converter
    6. 4.6  Electrical Characteristics: Dynamic Converter
    7. 4.7  Electrical Characteristics: Analog Input/Output and Reference
    8. 4.8  Electrical Characteristics: I-Channel to Q-Channel
    9. 4.9  Electrical Characteristics: Sampling Clock
    10. 4.10 Electrical Characteristics: AutoSync Feature
    11. 4.11 Electrical Characteristics: Digital Control and Output Pin
    12. 4.12 Electrical Characteristics: Power Supply
    13. 4.13 Electrical Characteristics: AC
    14. 4.14 Timing Requirements: Serial Port Interface
    15. 4.15 Timing Requirements: Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC- and DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-Command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read/Write Calibration Settings
        7. 5.3.3.7 Calibration and Power Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES and Non-DES Mode
      2. 5.4.2 Demux and Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power-Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power-Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC- and DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 The Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-Of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 The Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 The LVDS Outputs
        1. 6.1.3.1 Common-Mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1x00RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for the Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
    2. 7.2 Supply Voltage
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Specification Definitions
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

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発注情報

3 Pin Configuration and Functions

BGA Package
292-Pin NXA
Top-View

ADC12D1000RF ADC12D1600RF 30164401.gif
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 8.1 for more information.

3.1 Pin Attributes

Table 3-1 Analog Front-End and Clock Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION
NAME NO.
CLK+/- U2/V1 I
ADC12D1000RF ADC12D1600RF 30164412.gif
 Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled.
DCLK_RST+/- V2/W1 I
ADC12D1000RF ADC12D1600RF 30164429.gif
 Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1x00RFs to synchronize them with other ADC12D1x00RFs in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync.
RCLK+/- Y4/W5 I
ADC12D1000RF ADC12D1600RF 30164412.gif
 Reference Clock Input. When the AutoSync feature is active, and the ADC12D1x00RF is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM through Control Register (Addr: Eh).
RCOut1+/-
RCOut2+/-		 Y5/U6
V6/V7		 O
ADC12D1000RF ADC12D1600RF 30164430.gif
 Reference Clock Output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in Master or Slave Mode. They are used to drive the RCLK of another ADC12D1x00RF, to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1 and RCOut2 to the RCLK of another ADC12D1x00RF should be 100-Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable or disable this feature; default is disabled.
Rext+/- C3/D3 I/O
ADC12D1000RF ADC12D1600RF 30164434.gif
 External Reference Resistor terminals. A 3.3-kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used as a reference to trim internal circuits which affect the linearity of the converter; the value and precision of this resistor should not be compromised.
Rtrim+/- C1/D2 I/O
ADC12D1000RF ADC12D1600RF 30164434.gif
 Input Termination Trim Resistor terminals. A 3.3-kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100-Ω input impedance of VinI, VinQ and CLK. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not specified for such an alternate value.
Tdiode+/- E2/F3 Passive
ADC12D1000RF ADC12D1600RF 30164435.gif
 Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. It has not been fully characterized.
VBG B1 O
ADC12D1000RF ADC12D1600RF 30164408.gif
 Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing or sinking 100 µA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2-V LVDS common-mode voltage is selected; 0.8 V is the default.
VCMO C2 I/O
ADC12D1000RF ADC12D1600RF 30164406.gif
 Common-Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing or sinking up to 100 µA. For DC-coupled operation, this pin should be left floating or terminated into high impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer.
VinI+/-
VinQ+/-		 H1/J1
N1/M1		 I
ADC12D1000RF ADC12D1600RF 30164407.gif

Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Q-input may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6).

Each I- and Q-channel input has an internal common-mode bias that is disabled when DC-coupled Mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO Pin.

In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Q-channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set through the Control Register (Addr: 3h and Addr: Bh). The high and low full-scale input range setting in Non-ECM corresponds to the mid and minimum full-scale input range in ECM.

The input offset may also be adjusted in ECM.

Table 3-2 Control and Status Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION
NAME NO.
CAL D6 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. If this input is held high at the time of power on, the automatic power-on calibration cycle is inhibited until this input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration.
CalDly V4 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 Calibration Delay select. By setting this input logic-high or logic-low, the user can select the device to wait a longer or shorter amount of time, respectively, before the automatic power-on self-calibration is initiated. This feature is pin-controlled only and is always active during ECM and Non-ECM.
CalRun B5 O
ADC12D1000RF ADC12D1600RF 30164408.gif
 Calibration Running indication. This output is logic-high while the calibration sequence is executing. This output is logic-low otherwise.
DDRPh W4 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 DDR Phase select. This input, when logic-low, selects the 0° Data-to-DCLK phase relationship. When logic-high, it selects the 90° Data-to-DCLK phase relationship, that is, the DCLK transition indicates the middle of the valid data outputs. This pin only has an effect when the chip is in 1:2 Demuxed Mode, that is, the NDM pin is set to logic-low. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0° Mode.
DES V5 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, the DES Mode of operation is selected, meaning that the VinI input is sampled by both channels in a time-interleaved manner. The VinQ input is ignored. When this input is set to logic-low, the device is in Non-DES Mode, that is, the I- and Q-channels operate independently. In the Extended Control Mode (ECM), this input is ignored and DES Mode selection is controlled through the Control Register by the DES Bit (Addr: 0h, Bit 7); default is Non-DES Mode operation.
DNC D1, D7, E3, F4, W3, U7 — NONE Do Not Connect. These pins are used for internal purposes and should not be connected, that is, left floating. Do not ground.
ECE B3 I
ADC12D1000RF ADC12D1600RF 30164427.gif
 Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this signal is deasserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled through the control pins.
FSR Y3 I
ADC12D1000RF ADC12D1600RF 30164426.gif

Full-Scale input Range select. In Non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both I- and Q-channel inputs is set to the lower or higher FSR value, respectively. In the ECM, this input is ignored and the full-scale range of the I- and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. The high (lower) FSR value in Non-ECM corresponds to the mid (minimum) available selection in ECM; the FSR range in ECM is greater.

NC C7 — NONE Not Connected. This pin is not bonded and may be left floating or connected to any potential.
NDM A5 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non-ECM.
PDI
PDQ		 U3
V3		 I
ADC12D1000RF ADC12D1600RF 30164427.gif
 Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel. Setting either input to logic-low brings the respective I- or Q-channel to a operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to power down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively.
SCLK C5 I
ADC12D1000RF ADC12D1600RF 30164437.gif
 Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled.
SCS C4 I
ADC12D1000RF ADC12D1600RF 30164437.gif
 Serial Chip Select bar. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data which is present on SDI and to source serial data on SDO. When this signal is deasserted (logic-high), SDI is ignored and SDO is in tri-stated.
SDI B4 I
ADC12D1000RF ADC12D1600RF 30164437.gif
 Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low).
SDO A3 O
ADC12D1000RF ADC12D1600RF 30164408.gif
 Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is tri-stated when SCS is deasserted.
TPM A4 I
ADC12D1000RF ADC12D1600RF 30164426.gif
 Test Pattern Mode select. With this input at logic-high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12).

Table 3-3 Power and Ground Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION
NAME NO.
GND A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 — NONE Ground Return for the Analog circuitry.
GNDDR A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20 — NONE Ground Return for the Output Drivers.
GNDE A9, B8, C9, V9, W8, Y9 — NONE Ground Return for the Digital Encoder.
GNDTC F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 — NONE Ground Return for the Track-and-Hold and Clock circuitry.
VA A2, A6, B6, C6, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 — NONE Power Supply for the Analog circuitry. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply.
VbiasI J4, K2 — NONE Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100-nF capacitor through a low-resistance, low-inductance path to GND.
VbiasQ L2, M4 — NONE Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100-nF capacitor through a low-resistance, low-inductance path to GND.
VDR A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 — NONE Power Supply for the Output Drivers.
VE A8, B9, C8, V8, W9, Y8 — NONE Power Supply for the Digital Encoder.
VTC G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 — NONE Power Supply for the Track-and-Hold and Clock circuitry.

Table 3-4 High-Speed Digital Outputs

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION
NAME NO.
DCLKI+/-
DCLKQ+/-		 K19/K20
L19/L20		 O
ADC12D1000RF ADC12D1600RF 30164410.gif
 Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized.
DI11+/-
DI10+/-
DI9+/-
DI8+/-
DI7+/-
DI6+/-
DI5+/-
DI4+/-
DI3+/-
DI2+/-
DI1+/-
DI0+/-
·
DQ11+/-
DQ10+/-
DQ9+/-
DQ8+/-
DQ7+/-
DQ6+/-
DQ5+/-
DQ4+/-
DQ3+/-
DQ2+/-
DQ1+/-
DQ0+/-		 J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
B19/B20
B18/C17
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
W19/W20
W18/V17		 O
ADC12D1000RF ADC12D1600RF 30164410.gif
 I- and Q-channel Digital Data Outputs. In Non-Demux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, that is, the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver.
DId11+/-
DId10+/-
DId9+/-
DId8+/-
DId7+/-
DId6+/-
DId5+/-
DId4+/-
DId3+/-
DId2+/-
DId1+/-
DId0+/-
·
DQd11+/-
DQd10+/-
DQd9+/-
DQd8+/-
DQd7+/-
DQd6+/-
DQd5+/-
DQd4+/-
DQd3+/-
DQd2+/-
DQd1+/-
DQd0+/-		 A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
C10/D10
A10/B10
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
V10/U10
Y10/W10		 O
ADC12D1000RF ADC12D1600RF 30164410.gif
 Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are tri-stated. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, that is, the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver.
ORI+/-
ORQ+/-		 K17/K18
L17/L18		 O
ADC12D1000RF ADC12D1600RF 30164410.gif
 Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the over- or under-range condition exists, that is, the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current Data, with which it is clocked out. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. ORQ.(1)
(1) This pin and bit functionality is not tested in production test; performance is tested in the specified and default mode only.