SNAS519H July   2011  – August 2015 ADC12D1000RF , ADC12D1600RF

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Static Converter
    6. 4.6  Electrical Characteristics: Dynamic Converter
    7. 4.7  Electrical Characteristics: Analog Input/Output and Reference
    8. 4.8  Electrical Characteristics: I-Channel to Q-Channel
    9. 4.9  Electrical Characteristics: Sampling Clock
    10. 4.10 Electrical Characteristics: AutoSync Feature
    11. 4.11 Electrical Characteristics: Digital Control and Output Pin
    12. 4.12 Electrical Characteristics: Power Supply
    13. 4.13 Electrical Characteristics: AC
    14. 4.14 Timing Requirements: Serial Port Interface
    15. 4.15 Timing Requirements: Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC- and DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-Command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read/Write Calibration Settings
        7. 5.3.3.7 Calibration and Power Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES and Non-DES Mode
      2. 5.4.2 Demux and Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power-Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power-Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC- and DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 The Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-Of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 The Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 The LVDS Outputs
        1. 6.1.3.1 Common-Mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1x00RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for the Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
    2. 7.2 Supply Voltage
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Specification Definitions
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

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7 Power Supply Recommendations

7.1 System Power-on Considerations

Data-converter-based systems draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10-μF capacitor must be placed within one inch (2.5 cm) of the device power pins for each supply voltage. A 0.1-μF capacitor must be placed as close as possible to each supply pin, preferably within 0.5 cm. Leadless chip capacitors are preferred due to their low-lead inductance.

As is the case with all high-speed converters, the ADC12D1600RF device must be assumed to have little power supply noise-rejection. Any power supply used for digital circuitry in a system where a large amount of digital power is consumed must not be used to supply power to the ADC12D1600RF device. If not a dedicated supply, the ADC supplies must be the same supply used for other analog circuitry.

There are a couple important topics to consider associated with the system power-on event including configuration and calibration, and the Data Clock.

7.1.1 Power-on, Configuration, and Calibration

Following the application of power to the ADC12D1x00RF, several events must take place before the output from the ADC12D1x00RF is valid and at full performance; at least one full calibration must be executed with the device configured in the desired mode.

Following the application of power to the ADC12D1x00RF, there is a delay of tCalDly and then the Power-on Calibration is executed. This is why TI recommends setting the CalDly Pin through an external pullup or pulldown resistor. This ensures that the state of that input will be properly set at the same time that power is applied to the ADC and tCalDly will be a known quantity. For the purpose of this section, it is assumed that CalDly is set as recommended.

The Control Bits or Pins must be set or written to configure the ADC12D1x00RF in the desired mode. This must take place through either Extended Control Mode or Non-ECM (Pin Control Mode) before subsequent calibrations will yield an output at full performance in that mode. Some examples of modes include DES and Non-DES Mode, Demux and Non-demux Mode, and Full-Scale Range.

The simplest case is when device is in Non-ECM and the Control Pins are set by pullup and pulldown resistors, see Figure 7-1. For this case, the settings to the Control Pins ramp concurrently to the ADC voltage. Following the delay of tCalDly and the calibration execution time, tCAL, the output of the ADC12D1x00RF is valid and at full performance. If it takes longer than tCalDly for the system to stabilize at its operating temperature, TI recommends executing an on-command calibration at that time.

Another case is when the FPGA configures the Control Pins (Non-ECM) or writes to the SPI (ECM), see Figure 7-2. It is always necessary to comply with the Operating Ratings and Absolute Maximum ratings, that is, the Control Pins may not be driven below the ground or above the supply, regardless of what the voltage currently applied to the supply is. Therefore, it is not recommended to write to the Control Pins or SPI before power is applied to the ADC12D1x00RF. As long as the FPGA has completed writing to the Control Pins or SPI, the Power-on Calibration will result in a valid output at full performance. Once again, if it takes longer than tCalDly for the system to stabilize at its operating temperature, TI recommends executing an on-command calibration at that time.

Due to system requirements, it may not be possible for the FPGA to write to the Control Pins or SPI before the Power-on Calibration takes place, see Figure 7-3. It is not critical to configure the device before the Power-on Calibration, but it is critical to realize that the output for such a case is not at its full performance. Following an On-command Calibration, the device will be at its full performance.

ADC12D1000RF ADC12D1600RF 30164464.gifFigure 7-1 Power-On With Control Pins Set by Pullup and Pulldown Resistors
ADC12D1000RF ADC12D1600RF 30164465.gifFigure 7-2 Power-On With Control Pins Set by FPGA Pre-Power-On Cal
ADC12D1000RF ADC12D1600RF 30164466.gifFigure 7-3 Power-On With Control Pins Set by FPGA Post-Power-On Cal

7.1.2 Power-on and Data Clock (DCLK)

Many applications use the DCLK output for a system clock. For the ADC12D1x00RF, each I- and Q-channel has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that channel is powered-down or the DCLK Reset feature is used while the device is in Demux Mode. As the supply to the ADC12D1x00RF ramps, the DCLK also comes up, see this example from the ADC12D1600RFRB: Figure 7-4. While the supply is too low, there is no output at DCLK. As the supply continues to ramp, DCLK functions intermittently with irregular frequency, but the amplitude continues to track with the supply. Much below the low end of operating supply range of the ADC12D1x00RF, the DCLK is already fully operational.

ADC12D1000RF ADC12D1600RF 30164490.gifFigure 7-4 Supply and DCLK Ramping

7.2 Supply Voltage

The ADC12D1600RF device is specified to operate with nominal supply voltages of 1.9 V (VA, VTC, VE and VDR). For detailed information regarding the operating voltage minimums and maximums see Section 4.3.

The voltage on a pin (except VinI+/- and VinQ+/-), including a transient basis, must not have a voltage that is in excess of the supply voltage or below ground by more than 150 mV. A pin voltage that is higher than the supply or that is below ground can be a problem during start-up and shutdown of power. Ensure that the supplies to circuits driving any of the input pins, analog or digital, do not rise faster than the voltage at the ADC12D1600RF power pins.

The values in Section 4.1 must be strictly observed including during power up and power down. A power supply that produces a voltage spike at power turnon, turnoff, or both can destroy the ADC12D1600RF device. Many linear regulators produce output spiking at power on unless there is a minimum load provided. Active devices draw very little current until the supply voltages reach a few hundred millivolts. The result can be a turnon spike that destroys the ADC12D1600RF device, unless a minimum load is provided for the supply. A 100-Ω resistor at the regulator output provides a minimum output current during power up to ensure that no turnon spiking occurs. Whether a linear or switching regulator is used, TI recommends using a soft-start circuit to prevent overshoot of the supply.