SNAS480N May 2010 – August 2015 ADC12D1000 , ADC12D1600
PRODUCTION DATA.
SPACE
The 12-bit, 2.0/3.2 GSPS ADC12D1x00 device is the latest advance in TI's Ultra High-Speed ADC family and builds upon the features, architecture, and functionality of the 10-bit GHz family of ADCs.
The ADC12D1x00 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common-mode voltage.
The ADC12D1x00 is packaged in a leaded or lead-free 292-pin thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC12D1000 | BGA (292) | 27.00 mm × 27.00 mm |
ADC12D1600 |
Changes from M Revision (March 2013) to N Revision
Changes from L Revision (March 2013) to M Revision
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Layout Guidelines for more information.
PIN | I/O | EQUIVALENT CIRCUIT | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
CLK+/- | U2/V1 | I |
![]() |
Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the selected input is sampled on both transitions of this clock. This clock must be AC-coupled. |
DCLK_RST+/- | V2/W1 | I |
![]() |
Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1x00s to synchronize them with other ADC12D1x00s in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. |
RCLK+/- | Y4/W5 | I |
![]() |
Reference Clock Input. When the AutoSync feature is active, and the ADC12D1x00 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM through Control Register (Addr: Eh). |
RCOut1+/- RCOut2+/- |
Y5/U6 V6/V7 |
O |
![]() |
Reference Clock Output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in Master or Slave Mode. The signals are used to drive the RCLK of another ADC12D1x00, to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1 and RCOut2 to the RCLK of another ADC12D1x00 should be 100-Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable or disable this feature; default is disabled. |
Rext+/- | C3/D3 | I/O |
![]() |
External Reference Resistor terminals. A 3.3-kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used as a reference to trim internal circuits which affect the linearity of the converter; the value and precision of this resistor should not be compromised. |
Rtrim+/- | C1/D2 | I/O |
![]() |
Input Termination Trim Resistor terminals. A 3.3-kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100-Ω input impedance of VinI, VinQ and CLK. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not ensured for such an alternate value. |
Tdiode+/- | E2/F3 | Passive |
![]() |
Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. It has not been fully characterized. |
VBG | B1 | O |
![]() |
Bandgap Voltage Output or LVDS Common-mode Voltage Select. This pin provides a buffered version of the bandgap output voltage and is capable of sourcing and sinking 100 µA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2-V LVDS common-mode voltage is selected; 0.8 V is the default. |
VCMO | C2 | I/O |
![]() |
Common-Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be held at logic-low level. This pin is capable of sourcing and sinking up to 100 µA. For DC-coupled operation, this pin should be left floating or terminated into high-impedance. In DC-coupled Mode, this pin provides an output voltage which is the optimal common-mode voltage for the input signal and should be used to set the common-mode voltage of the driving buffer. |
VinI+/- VinQ+/- |
H1/J1 N1/M1 |
I |
![]() |
Differential signal I- and Q-inputs. In the Non-Dual Edge Sampling (Non-DES) Mode, each I- and Q-input is sampled and converted by its respective channel with each positive transition of the CLK input. In Non-ECM (Non-Extended Control Mode) and DES Mode, both channels sample the I-input. In Extended Control Mode (ECM), the Q-input may optionally be selected for conversion in DES Mode by the DEQ Bit (Addr: 0h, Bit 6). Each I- and Q-channel input has an internal common mode bias that is disabled when DC-coupled Mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO Pin. In Non-ECM, the full-scale range of these inputs is determined by the FSR Pin; both I- and Q-channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set through the Control Register (Addr: 3h and Addr: Bh). The high and low full-scale input range setting in Non-ECM corresponds to the mid and minimum full-scale input range in ECM. The input offset may also be adjusted in ECM. |
PIN | I/O | EQUIVALENT CIRCUIT | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
CAL | D6 | I |
![]() |
Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. If this input is held high at the time of power on, the automatic power-on calibration cycle is inhibited until this input is cycled low-then-high. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. |
CalDly | V4 | I |
![]() |
Calibration Delay select. By setting this input logic-high or logic-low, the user can select the device to wait a longer or shorter amount of time, respectively, before the automatic power-on self-calibration is initiated. This feature is pin-controlled only and is always active during ECM and Non-ECM. |
CalRun | B5 | O |
![]() |
Calibration Running indication. This output is logic-high while the calibration sequence is executing. This output is logic-low otherwise. |
DDRPh | W4 | I |
![]() |
DDR Phase select. This input, when logic-low, selects the 0° Data-to-DCLK phase relationship. When logic-high, it selects the 90° Data-to-DCLK phase relationship, that is, the DCLK transition indicates the middle of the valid data outputs. This pin only has an effect when the chip is in 1:2 Demuxed Mode, that is, the NDM pin is set to logic-low. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0° Mode. |
DES | V5 | I |
![]() |
Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, the DES Mode of operation is selected, meaning that the VinI input is sampled by both channels in a time-interleaved manner. The VinQ input is ignored. When this input is set to logic-low, the device is in Non-DES Mode, that is, the I- and Q-channels operate independently. In the Extended Control Mode (ECM), this input is ignored and DES Mode selection is controlled through the Control Register by the DES Bit (Addr: 0h, Bit 7); default is Non-DES Mode operation. |
DNC | D1, D7, E3, F4, W3, U7 | — | NONE | Do Not Connect. These pins are used for internal purposes and should not be connected, that is, left floating. Do not ground. |
ECE | B3 | I |
![]() |
Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this signal is deasserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled through the control pins. |
FSR | Y3 | I |
![]() |
Full-Scale input Range select. In Non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both I- and Q-channel inputs is set to the lower or higher FSR value, respectively. In the ECM, this input is ignored and the full-scale range of the I- and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. The high (lower) FSR value in Non-ECM corresponds to the mid (min) available selection in ECM; the FSR range in ECM is greater. |
NC | C7 | — | NONE | Not Connected. This pin is not bonded and may be left floating or connected to any potential. |
NDM | A5 | I |
![]() |
Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non-ECM. |
PDI PDQ |
U3 V3 |
I |
![]() |
Power-down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel. Setting either input to logic-low brings the respective I- or Q-channel to an operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to power-down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. |
SCLK | C5 | I |
![]() |
Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled. |
SCS | C4 | I |
![]() |
Serial Chip Select bar. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data which is present on SDI and to source serial data on SDO. When this signal is deasserted (logic-high), SDI is ignored and SDO is at TRI-STATE. |
SDI | B4 | I |
![]() |
Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). |
SDO | A3 | O |
![]() |
Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is at TRI-STATE when SCS is deasserted. |
TPM | A4 | I |
![]() |
Test Pattern Mode select. With this input at logic-high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the Test Pattern Mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12). |
PIN | I/O | EQUIVALENT CIRCUIT | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
GND | A1, A7, B2, B7, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, H8:N13 | — | NONE | Ground Return for the Analog circuitry. |
GNDDR | A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20 | — | NONE | Ground Return for the Output Drivers. |
GNDE | A9, B8, C9, V9, W8, Y9 | — | NONE | Ground Return for the Digital Encoder. |
GNDTC | F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 | — | NONE | Ground Return for the Track-and-Hold and Clock circuitry. |
VA | A2, A6, B6, C6, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 | — | NONE | Power Supply for the Analog circuitry. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply. |
VbiasI | J4, K2 | — | NONE | Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100-nF capacitor through a low-resistance, low-inductance path to GND. |
VbiasQ | L2, M4 | — | NONE | Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100-nF capacitor through a low-resistance, low-inductance path to GND. |
VDR | A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 | — | NONE | Power Supply for the Output Drivers. |
VE | A8, B9, C8, V8, W9, Y8 | — | NONE | Power Supply for the Digital Encoder. |
VTC | G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 | — | NONE | Power Supply for the Track-and-Hold and Clock circuitry. |
PIN | I/O | EQUIVALENT CIRCUIT | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
DCLKI+/- DCLKQ+/- |
K19/K20 L19/L20 |
O |
![]() |
Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the sampling clock rate, respectively. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. |
DI11+/- DI10+/- DI9+/- DI8+/- DI7+/- DI6+/- DI5+/- DI4+/- DI3+/- DI2+/- DI1+/- DI0+/- · DQ11+/- DQ10+/- DQ9+/- DQ8+/- DQ7+/- DQ6+/- DQ5+/- DQ4+/- DQ3+/- DQ2+/- DQ1+/- DQ0+/- |
J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 B19/B20 B18/C17 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 W19/W20 W18/V17 |
O |
![]() |
I- and Q-channel Digital Data Outputs. In Non-Demux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, that is, the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
DId11+/- DId10+/- DId9+/- DId8+/- DId7+/- DId6+/- DId5+/- DId4+/- DId3+/- DId2+/- DId1+/- DId0+/- · DQd11+/- DQd10+/- DQd9+/- DQd8+/- DQd7+/- DQd6+/- DQd5+/- DQd4+/- DQd3+/- DQd2+/- DQd1+/- DQd0+/- |
A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 C10/D10 A10/B10 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 V10/U10 Y10/W10 |
O |
![]() |
Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are at TRI-STATE. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non-delayed data, that is, the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
ORI+/- ORQ+/- |
K17/K18 L17/L18 |
O |
![]() |
Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the over- or under-range condition exists, that is, the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current Data, with which it is clocked out. If used, each of these outputs should always be terminated with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage (VA, VTC, VDR, VE) | 2.2 | V | ||
Supply Difference max(VA/TC/DR/E) - min(VA/TC/DR/E) |
0 | 100 | mV | |
Voltage on Any Input Pin (except VIN+/-) |
–0.15 | VA + 0.15 | V | |
VIN+/- Voltage Range | –0.5 | 2.5 | V | |
Ground Difference max(GNDTC/DR/E) - min(GNDTC/DR/E) |
0 | 100 | mV | |
Input Current at Any Pin(2) | –50 | 50 | mA | |
ADC12D1000 Package Power Dissipation at TA ≤ 75°C(2) | 4.06 | W | ||
ADC12D1600 Package Power Dissipation at TA ≤ 65°C(2) | 4.37 | W | ||
Storage Temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine Model | ±250 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TA | Ambient Temperature | ADC12D1000 (Standard JEDEC thermal model) | –40 | 75 | °C | |
ADC12D1600 (Standard JEDEC thermal model) | –40 | 65 | °C | |||
ADC12D1x00 (Enhanced thermal model or heatsink) | –40 | 85 | °C | |||
TJ | Junction Temperature Range(4) | ADC12D1000 Junction Temperature Range | 140 | °C | ||
ADC12D1600 Junction Temperature Range | 135 | °C | ||||
Supply Voltage (VA, VTC, VE) | 1.8 | 2 | V | |||
Driver Supply Voltage (VDR) | 1.8 | VA | V | |||
VIN+/- Voltage Range(2) | (DC-coupled) | –0.4 | 2.4 | V | ||
VIN+/- Differential Voltage(3) | (DC-coupled at 100% duty cycle) | 1 | V | |||
(DC-coupled at 20% duty cycle) | 2 | |||||
(DC-coupled at 10% duty cycle) | 2.8 | |||||
VIN+/- Current Range(3) | (AC-coupled) | –50 | 50 | mA peak | ||
VIN+/- Power | (maintaining common-mode voltage, AC-coupled) | 15.3 | dBm | |||
(not maintaining common-mode voltage, AC-coupled) | 17.1 | |||||
Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) |
0 | V | ||||
CLK+/- Voltage Range | 0 | VA | V | |||
Differential CLK Amplitude | 0.4 | 2 | VP-P | |||
VCMI Common Mode Input Voltage | VCMO – 150 | VCMO +150 | mV |
THERMAL METRIC(1) | ADC12D1000, ADC12D1600 | UNIT | |
---|---|---|---|
NXA (BGA) | |||
292 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 16 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 2.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Resolution with No Missing Codes | TA = TMIN to TMAX | 12 | bits | ||||
INL | Integral Non-Linearity (Best fit) |
1-MHz DC-coupled over-ranged sine wave | TA = 25°C | ±2.5 | LSB | ||
TA = TMIN to TMAX | ±4.8 | ||||||
DNL | Differential Non-Linearity | 1-MHz DC-coupled over-ranged sine wave | TA = 25°C | ±0.4 | LSB | ||
TA = TMIN to TMAX | ±0.9 | ||||||
VOFF | Offset Error | 5 | LSB | ||||
VOFF_ADJ | Input Offset Adjustment Range | Extended Control Mode | ±45 | mV | |||
PFSE | Positive Full-Scale Error | See(4). TA = TMIN to TMAX | ±25 | mV | |||
NFSE | Negative Full-Scale Error | See(4). TA = TMIN to TMAX | ±25 | mV | |||
Out-of-Range Output Code(5) | (VIN+) − (VIN−) > + Full Scale, TA = TMIN to TMAX | 4095 | |||||
(VIN+) − (VIN−) < − Full Scale, TA = TMIN to TMAX | 0 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
FPBW | Full Power Bandwidth | Non-DES Mode | 2.8 | GHz | |||
DESI, DESQ Mode | 1.25 | GHz | |||||
DESIQ Mode | 1.75 | GHz | |||||
Gain Flatness | NON-DES MODE | ||||||
D.C. to Fs/2 | ADC12D1000 | 0.35 | dB | ||||
ADC12D1600 | 0.5 | ||||||
D.C. to Fs | ADC12D1000 | 0.5 | dB | ||||
ADC12D1600 | 1 | ||||||
DESI, DESQ MODE | |||||||
D.C. to Fs/2 | ADC12D1000 | 2.4 | dB | ||||
ADC12D1600 | 4 | ||||||
DESIQ MODE | |||||||
D.C. to Fs/2 | ADC12D1000 | 1.9 | dB | ||||
ADC12D1600 | 2 | ||||||
CER | Code Error Rate | 10–18 | Error/Sample | ||||
NPR | Noise Power Ratio | See(1) | ADC12D1000 | 49.5 | dB | ||
ADC12D1600 | 48.5 | ||||||
IMD3 | 3rd order Intermodulation Distortion | FIN1 = 1212.52 MHz at -7dBFS | ADC12D1000 | –66 | dBFS | ||
ADC12D1600 | –63 | ||||||
FIN2 = 1217.52 MHz at -7dBFS DESIQ Mode |
ADC12D1000 | –59 | dBc | ||||
ADC12D1600 | –56 | ||||||
Noise Floor Density | 50Ω single-ended termination, DES Mode | ADC12D1000 | –152.6 | dBm/Hz | |||
ADC12D1600 | –153.6 | ||||||
ADC12D1000 | –151.6 | dBFS/Hz | |||||
ADC12D1600 | –152.6 | ||||||
Wideband input, DES Mode(2) | ADC12D1000 | –151.5 | dBm/Hz | ||||
ADC12D1600 | –152.6 | ||||||
ADC12D1000 | –150.5 | dBFS/Hz | |||||
ADC12D1600 | –151.6 | ||||||
NON-DES MODE(2)(2) | |||||||
ENOB | Effective Number of Bits | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 9.6 | bits | ||
ADC12D1600 | 9.4 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
9.5 8.7 |
bits | ||||
ADC12D1600 TA = TMIN to TMAX |
9.4 8.6 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
9.4 8.7 |
bits | ||||
ADC12D1600 TA = TMIN to TMAX |
9.3 8.6 |
||||||
AIN = 998 MHz at –0.5 dBFS | 8.9 | bits | |||||
AIN = 1448 MHz at –0.5 dBFS | 8.6 | bits | |||||
SINAD | Signal-to-Noise Plus Distortion Ratio | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 59.7 | dB | ||
ADC12D1600 | 58.2 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
59 54.1 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
58 53.5 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
58.2 54.1 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
57.8 53.5 |
||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 55.4 | dB | ||||
ADC12D1600 | 55.1 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 53.6 | dB | ||||
ADC12D1600 | 53.8 | ||||||
SNR | Signal-to-Noise Ratio | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 60.2 | dB | ||
ADC12D1600 | 58.5 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
59.7 55.1 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
58.7 54.6 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
58.7 55.1 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
58.5 54.6 |
||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 56.3 | dB | ||||
ADC12D1600 | 56.5 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 54.1 | dB | ||||
ADC12D1600 | 55 | ||||||
THD | Total Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –68.7 | dB | ||
ADC12D1600 | –70.3 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
–67 –61 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
–66.6 –60 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
–67.4 –61 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
–66 –60 |
||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –62.9 | dB | ||||
ADC12D1600 | –60.8 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | –63 | dB | ||||
ADC12D1600 | –60 | ||||||
2nd Harm | Second Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –75.7 | dBc | ||
ADC12D1600 | –75 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 | –75.7 | dBc | ||||
ADC12D1600 | –80 | ||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | –79.8 | dBc | ||||
ADC12D1600 | –71 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –70 | dBc | ||||
ADC12D1600 | –73 | ||||||
AIN = 1448 MHz at –0.5 dBFS | –67 | dBc | |||||
3rd Harm | Third Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –71 | dBc | ||
ADC12D1600 | –74 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 | –68.4 | dBc | ||||
ADC12D1600 | –68 | ||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | –68.7 | dBc | ||||
ADC12D1600 | –69 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –66 | dBc | ||||
ADC12D1600 | –62 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | –67 | dBc | ||||
ADC12D1600 | –61 | ||||||
SFDR | Spurious-Free Dynamic Range | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 71 | dBc | ||
ADC12D1600 | 70.3 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
68.4 61 |
dBc | ||||
ADC12D1600 TA = TMIN to TMAX |
68 60 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
68.7 61 |
dBc (min) | ||||
ADC12D1600 TA = TMIN to TMAX |
68.2 60 |
||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 66 | dBc | ||||
ADC12D1600 | 62 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 67 | dBc | ||||
ADC12D1600 | 61.9 | ||||||
DES MODE(2)(2)(2) | |||||||
ENOB | Effective Number of Bits | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 9.5 | bits | ||
ADC12D1600 | 9.4 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
9.4 8.7 |
bits | ||||
ADC12D1600 TA = TMIN to TMAX |
9.2 8.6 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | 9.2 | bits | ||||
ADC12D1600 | 9.1 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 8.8 | bits | ||||
ADC12D1600 | 8.5 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 8.6 | bits | ||||
ADC12D1600 | 8.5 | ||||||
SINAD | Signal-to-Noise Plus Distortion Ratio | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 59 | dB | ||
ADC12D1600 | 58.2 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
58.6 54 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
57 53.5 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | 57.3 | dB | ||||
ADC12D1600 | 56.9 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 54.5 | dB | ||||
ADC12D1600 | 52.7 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 53.9 | dB | ||||
ADC12D1600 | 52.7 | ||||||
SNR | Signal-to-Noise Ratio | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 59.2 | dB | ||
ADC12D1600 | 58.6 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
58.9 55.3 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
57.9 54.6 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | 58.3 | dB | ||||
ADC12D1600 | 57.6 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 55.9 | dB | ||||
ADC12D1600 | 53.6 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 54.2 | dB | ||||
ADC12D1600 | 53.3 | ||||||
THD | Total Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –74 | dB | ||
ADC12D1600 | –68.2 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
–71.2 –60 |
dB | ||||
ADC12D1600 TA = TMIN to TMAX |
–64.6 –60 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | –63.8 | dB | ||||
ADC12D1600 | –66.3 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –60 | dB | ||||
ADC12D1600 | –60 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | –65 | dB | ||||
ADC12D1600 | –61.7 | ||||||
2nd Harm | Second Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –82 | dBc | ||
ADC12D1600 | –77.3 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 | –82 | dBc | ||||
ADC12D1600 | –82.7 | ||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | –72 | dBc | ||||
ADC12D1600 | –71.6 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –63.2 | dBc | ||||
ADC12D1600 | –63 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | –75 | dBc | ||||
ADC12D1600 | –75.6 | ||||||
3rd Harm | Third Harmonic Distortion | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | –82 | dBc | ||
ADC12D1600 | –69.8 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 | –73 | dBc | ||||
ADC12D1600 | –65.3 | ||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | –65 | dBc | ||||
ADC12D1600 | –67.3 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | –65 | dBc | ||||
ADC12D1600 | –63 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | –67 | dBc | ||||
ADC12D1600 | –62.4 | ||||||
SFDR | Spurious-Free Dynamic Range | AIN = 125 MHz at –0.5 dBFS | ADC12D1000 | 69 | dBc | ||
ADC12D1600 | 69.8 | ||||||
AIN = 248 MHz at –0.5 dBFS | ADC12D1000 TA = TMIN to TMAX |
69 60 |
dBc | ||||
ADC12D1600 TA = TMIN to TMAX |
65.3 60 |
||||||
AIN = 498 MHz at –0.5 dBFS | ADC12D1000 | 65 | dBc | ||||
ADC12D1600 | 67.3 | ||||||
AIN = 998 MHz at –0.5 dBFS | ADC12D1000 | 64 | dBc | ||||
ADC12D1600 | 60.2 | ||||||
AIN = 1448 MHz at –0.5 dBFS | ADC12D1000 | 66 | dBc | ||||
ADC12D1600 | 60 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG INPUTS | |||||||
VIN_FSR | Analog Differential Input Full Scale Range | NON-EXTENDED CONTROL MODE | |||||
FSR Pin Low | ADC12D1000 TA = TMIN to TMAX |
540 |
600 |
660 |
mVP-P | ||
ADC12D1600 TA = TMIN to TMAX |
540 |
600 |
660 |
mVP-P | |||
FSR Pin High | ADC12D1000 TA = TMIN to TMAX |
740 |
800 |
860 |
mVP-P | ||
ADC12D1600 TA = TMIN to TMAX |
740 |
800 |
860 |
mVP-P | |||
EXTENDED CONTROL MODE | |||||||
FM(14:0) = 0000h | 600 | mVP-P | |||||
FM(14:0) = 4000h (default) | 800 | mVP-P | |||||
FM(14:0) = 7FFFh | 1000 | mVP-P | |||||
CIN | Analog Input Capacitance, Non-DES Mode(1)(2) |
Differential | 0.02 | pF | |||
Each input pin to ground | 1.6 | pF | |||||
Analog Input Capacitance, DES Mode(1)(2) |
Differential | 0.08 | pF | ||||
Each input pin to ground | 2.2 | pF | |||||
RIN | Differential Input Resistance | ADC12D1000 TA = TMIN to TMAX |
91 |
100 |
109 |
Ω | |
ADC12D1600 TA = TMIN to TMAX |
91 |
100 |
109 |
Ω | |||
COMMON-MODE OUTPUT | |||||||
VCMO | Common-Mode Output Voltage | ICMO = ±100 µA | ADC12D1000 TA = TMIN to TMAX |
1.15 |
1.25 |
1.35 |
V |
ADC12D1600 TA = TMIN to TMAX |
1.15 |
1.25 |
1.35 |
V | |||
TC_VCMO | Common-Mode Output Voltage Temperature Coefficient | ICMO = ±100 µA | 38 | ppm/°C | |||
VCMO_LVL | VCMO input threshold to set DC-coupling Mode |
0.63 | V | ||||
CL_VCMO | Maximum VCMO Load Capacitance | See(1) | 80 | pF | |||
BANDGAP REFERENCE | |||||||
VBG | Bandgap Reference Output Voltage | IBG = ±100 µA | ADC12D1000 TA = TMIN to TMAX |
1.15 |
1.25 |
1.35 |
V |
ADC12D1600 TA = TMIN to TMAX |
1.15 |
1.25 |
1.35 |
V | |||
TC_VBG | Bandgap Reference Voltage Temperature Coefficient | IBG = ±100 µA | 32 | ppm/°C | |||
CL_VBG | Maximum Bandgap Reference load Capacitance | See(1) | 80 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Offset Match | 2 | LSB | ||||
Positive Full-Scale Match | Zero offset selected in Control Register |
2 | LSB | |||
Negative Full-Scale Match | Zero offset selected in Control Register |
2 | LSB | |||
Phase Matching (I, Q) | fIN = 1 GHz | < 1 | Degree | |||
X-TALK | Crosstalk from I-channel (Aggressor) to Q-channel (Victim) | Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. |
−70 | dB | ||
Crosstalk from Q-channel (Aggressor) to I-channel (Victim) | Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. |
−70 | dB |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN_CLK | Differential Sampling Clock Input Level(2) | Sine Wave Clock Differential Peak-to-Peak |
ADC12D1000 TA = TMIN to TMAX |
0.4 |
0.6 |
2 |
VP-P |
ADC12D1600 TA = TMIN to TMAX |
0.4 |
0.6 |
2 |
VP-P | |||
Square Wave Clock Differential Peak-to-Peak |
ADC12D1000 TA = TMIN to TMAX |
0.4 |
0.6 |
2 |
VP-P (min) | ||
ADC12D1600 TA = TMIN to TMAX |
0.4 |
0.6 |
2 |
VP-P (max) | |||
CIN_CLK | Sampling Clock Input Capacitance(1) | Differential | 0.1 | pF | |||
Each input to ground | 1 | pF | |||||
RIN_CLK | Sampling Clock Differential Input Resistance | 100 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN_RCLK | Differential RCLK Input Level | Differential Peak-to-Peak | 360 | mVP-P | ||
CIN_RCLK | RCLK Input Capacitance | Differential | 0.1 | pF | ||
Each input to ground | 1 | |||||
RIN_RCLK | RCLK Differential Input Resistance | 100 | Ω | |||
IIH_RCLK | Input Leakage Current; VIN = VA |
22 | µA | |||
IIL_RCLK | Input Leakage Current; VIN = GND |
–33 | µA | |||
VO_RCOUT | Differential RCOut Output Voltage | 360 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS) | |||||||
VIH | Logic High Input Voltage | TA = TMIN to TMAX | 0.7×VA | V | |||
VIL | Logic Low Input Voltage | TA = TMIN to TMAX | 0.3×VA | V | |||
IIH | Input Leakage Current; VIN = VA |
0.02 | μA | ||||
IIL | Input Leakage Current; VIN = GND |
FSR, CalDly, CAL, NDM, TPM, DDRPh, DES | –0.02 | μA | |||
SCS, SCLK, SDI | –17 | μA | |||||
PDI, PDQ, ECE | –38 | μA | |||||
CIN_DIG | Digital Control Pin Input Capacitance(1) | Measured from each control pin to GND | 1.5 | pF | |||
DIGITAL OUTPUT PINS (DATA, DCLKI, DCLKQ, ORI, ORQ) | |||||||
VOD | LVDS Differential Output Voltage | VBG = Floating, OVS = High | ADC12D1000 TA = TMIN to TMAX |
400 |
630 |
800 |
mVP-P |
ADC12D1600 TA = TMIN to TMAX |
400 |
630 |
800 |
mVP-P | |||
VBG = Floating, OVS = Low | ADC12D1000 TA = TMIN to TMAX |
230 |
460 |
630 |
mVP-P | ||
ADC12D1600 TA = TMIN to TMAX |
230 |
460 |
630 |
mVP-P | |||
VBG = VA, OVS = High | 670 | mVP-P | |||||
VBG = VA, OVS = Low | 500 | mVP-P | |||||
ΔVO DIFF | Change in LVDS Output Swing Between Logic Levels | ±1 | mV | ||||
VOS | Output Offset Voltage | VBG = Floating | 0.8 | V | |||
VBG = VA | 1.2 | V | |||||
ΔVOS | Output Offset Voltage Change Between Logic Levels | ±1 | mV | ||||
IOS | Output Short-Circuit Current | VBG = Floating; D+ and D− connected to 0.8 V |
±4 | mA | |||
ZO | Differential Output Impedance | 100 | Ω | ||||
VOH | Logic High-Output Level | CalRun, IOH = −100 µA(2), SDO, IOH = −400 µA(2) |
1.65 | V | |||
VOL | Logic Low Output Level | CalRun, IOL = 100 µA(2), SDO, IOL = 400 µA(2) |
0.15 | V | |||
DIFFERENTIAL DCLK RESET PINS (DCLK_RST) | |||||||
VCMI_DRST | DCLK_RST Common-Mode Input Voltage | 1.25 | V | ||||
VID_DRST | Differential DCLK_RST Input Voltage | VIN_CLK | VP-P | ||||
RIN_DRST | Differential DCLK_RST Input Resistance | See(1) | 100 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IA | Analog Supply Current | PDI = PDQ = Low | ADC12D1000 | 1110 | mA | ||
ADC12D1600 | 1235 | ||||||
PDI = Low; PDQ = High | ADC12D1000 | 610 | mA | ||||
ADC12D1600 | 670 | ||||||
PDI = High; PDQ = Low | ADC12D1000 | 610 | mA | ||||
ADC12D1600 | 670 | ||||||
PDI = PDQ = High | 15 | mA | |||||
ITC | Track-and-Hold and Clock Supply Current | PDI = PDQ = Low | ADC12D1000 | 400 | mA | ||
ADC12D1600 | 470 | ||||||
PDI = Low; PDQ = High | ADC12D1000 | 240 | mA | ||||
ADC12D1600 | 280 | ||||||
PDI = High; PDQ = Low | ADC12D1000 | 240 | mA | ||||
ADC12D1600 | 280 | ||||||
PDI = PDQ = High | 4 | mA | |||||
IDR | Output Driver Supply Current | PDI = PDQ = Low | ADC12D1000 | 305 | mA | ||
ADC12D1600 | 325 | ||||||
PDI = Low; PDQ = High | ADC12D1000 | 160 | mA | ||||
ADC12D1600 | 170 | ||||||
PDI = High; PDQ = Low | ADC12D1000 | 160 | mA | ||||
ADC12D1600 | 170 | ||||||
PDI = PDQ = High | 3 | mA | |||||
IE | Digital Encoder Supply Current | PDI = PDQ = Low | ADC12D1000 | 80 | mA | ||
ADC12D1600 | 140 | ||||||
PDI = Low; PDQ = High | ADC12D1000 | 40 | mA | ||||
ADC12D1600 | 70 | ||||||
PDI = High; PDQ = Low | ADC12D1000 | 40 | mA | ||||
ADC12D1600 | 70 | ||||||
PDI = PDQ = High | 1 | mA | |||||
ITOTAL | Total Supply Current | 1:2 Demux Mode PDI = PDQ = Low |
ADC12D1000 TA = TMIN to TMAX |
1895 |
2105 |
mA | |
ADC12D1600 TA = TMIN to TMAX |
2170 |
2310 |
|||||
Non-Demux Mode PDI = PDQ = Low |
ADC12D1000 | 1780 | mA | ||||
ADC12D1600 | 2040 | ||||||
PC | Power Consumption | 1:2 Demux Mode | |||||
PDI = PDQ = Low | ADC12D1000 TA = TMIN to TMAX |
3.60 |
4 |
W | |||
ADC12D1600 TA = TMIN to TMAX |
4.12 |
4.4 |
|||||
PDI = Low; PDQ = High | ADC12D1000 | 1.99 | W | ||||
ADC12D1600 | 2.26 | ||||||
PDI = High; PDQ = Low | ADC12D1000 | 1.99 | W | ||||
ADC12D1600 | 2.26 | ||||||
PDI = PDQ = High | 43 | mW | |||||
Non-Demux Mode PDI = PDQ = Low |
ADC12D1000 | 3.38 | W | ||||
ADC12D1600 | 3.88 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SAMPLING CLOCK (CLK) | |||||||
fCLK (max) | Maximum Sampling Clock Frequency | ADC12D1000 TA = TMIN to TMAX |
1.0 | GHz | |||
ADC12D1600 TA = TMIN to TMAX |
1.6 | ||||||
fCLK (min) | Minimum Sampling Clock Frequency | Non-DES Mode; LFS = 0b | ADC12D1000 TA = TMIN to TMAX |
300 | MHz | ||
ADC12D1600 TA = TMIN to TMAX |
300 | ||||||
Non-DES Mode; LFS = 1b, TA = TMIN to TMAX | 150 | MHz | |||||
DES Mode, TA = TMIN to TMAX | 500 | MHz | |||||
Sampling Clock Duty Cycle | fCLK(min) ≤ fCLK ≤ fCLK(max)(2) | ADC12D1000 TA = TMIN to TMAX |
20% |
50% |
80% |
||
ADC12D1600 TA = TMIN to TMAX |
20% |
50% |
80% |
||||
tCL | Sampling Clock Low Time | See(1) | ADC12D1000 TA = TMIN to TMAX |
200 |
500 | ps | |
ADC12D1600 TA = TMIN to TMAX |
125 |
312.5 | |||||
tCH | Sampling Clock High Time | See(1) | ADC12D1000 TA = TMIN to TMAX |
200 |
500 | p | |
ADC12D1600 TA = TMIN to TMAX |
125 |
312.5 | |||||
DATA CLOCK (DCLKI, DCLKQ) | |||||||
DCLK Duty Cycle | See(1) | ADC12D1000 TA = TMIN to TMAX |
45% |
50% |
55% |
||
ADC12D1600 TA = TMIN to TMAX |
45% |
50% |
55% |
||||
tSR | Setup Time DCLK_RST± | See(2) | 45 | ps | |||
tHR | Hold Time DCLK_RST± | See(2) | 45 | ps | |||
tPWR | Pulse Width DCLK_RST± | See(1), TA = TMIN to TMAX | 5 | Sampling Clock Cycles | |||
tSYNC_DLY | DCLK Synchronization Delay | 90° Mode(1), TA = TMIN to TMAX | 4 | Sampling Clock Cycles | |||
0° Mode(1), TA = TMIN to TMAX | 5 | ||||||
tLHT | Differential Low-to-High Transition Time | 10%-to-90%, CL = 2.5 pF | 200 | ps | |||
tHLT | Differential High-to-Low Transition Time | 10%-to-90%, CL = 2.5 pF | 200 | ps | |||
tSU | Data-to-DCLK Setup Time | 90° Mode(1) | ADC12D1000 | 870 | ps | ||
ADC12D1600 | 500 | ||||||
tH | DCLK-to-Data Hold Time | 90° Mode(1) | ADC12D1000 | 870 | ps | ||
ADC12D1600 | 500 | ||||||
tOSK | DCLK-to-Data Output Skew | 50% of DCLK transition to 50% of Data transition(1) | ±50 | ps | |||
DATA INPUT-TO-OUTPUT | |||||||
tAD | Aperture Delay | Sampling CLK+ Rise to Acquisition of Data | 1.15 | ns | |||
tAJ | Aperture Jitter | 0.2 | ps (rms) | ||||
tOD | Sampling Clock-to Data Output Delay (in addition to Latency) | 50% of Sampling Clock transition to 50% of Data transition | 3.2 | ns | |||
tLAT | Latency in 1:2 Demux Non-DES Mode(1) | DI, DQ Outputs, TA = TMIN to TMAX | 34 | Sampling Clock Cycles | |||
DId, DQd Outputs, TA = TMIN to TMAX | 35 | ||||||
Latency in 1:4 Demux DES Mode(1) | DI Outputs, TA = TMIN to TMAX | 34 | |||||
DQ Outputs, TA = TMIN to TMAX | 34.5 | ||||||
DId Outputs, TA = TMIN to TMAX | 35 | ||||||
DQd Outputs, TA = TMIN to TMAX | 35.5 | ||||||
Latency in Non-Demux Non-DES Mode(1) | DI Outputs, TA = TMIN to TMAX | 34 | |||||
DQ Outputs, TA = TMIN to TMAX | 34 | ||||||
Latency in Non-Demux DES Mode(1) | DI Outputs, TA = TMIN to TMAX | 34 | |||||
DQ Outputs, TA = TMIN to TMAX | 34.5 | ||||||
tORR | Over-Range Recovery Time | Differential VIN step from ±1.2 V to 0 V to accurate conversion | 1 | Sampling Clock Cycle | |||
tWU | Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion) | Non-DES Mode(1) | 500 | ns | |||
DES Mode(1) | 1 | µs |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSCLK | Serial Clock Frequency | See(1) | 15 | MHz | ||
Serial Clock Low Time | TA = TMIN to TMAX | 30 | ns | |||
Serial Clock High Time | TA = TMIN to TMAX | 30 | ns | |||
tSSU | Serial Data-to-Serial Clock Rising Setup Time | See(1) | 2.5 | ns | ||
tSH | Serial Data-to-Serial Clock Rising Hold Time | See(1) | 1 | ns | ||
tSCS | SCS-to-Serial Clock Rising Setup Time | 2.5 | ns | |||
tHCS | SCS-to-Serial Clock Falling Hold Time | 1.5 | ns | |||
tBSU | Bus turnaround time | 10 | ns |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
tCAL | Calibration Cycle Time | CSS = 0b | 5.2·107 | Sampling Clock Cycles | ||
CSS = 1b | ||||||
tCAL_L | CAL Pin Low Time | See(1), TA = TMIN to TMAX | 1280 | Sampling Clock Cycles | ||
tCAL_H | CAL Pin High Time | See(1), TA = TMIN to TMAX | 1280 | |||
tCalDly | Calibration delay determined by CalDly Pin(1) | CalDly = Low, TA = TMIN to TMAX | 224 | Sampling Clock Cycles | ||
CalDly = High, TA = TMIN to TMAX | 230 |
The ADC12D1x00 is a versatile A/D converter with an innovative architecture, which permits very high-speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in Application Information. This section covers an overview, a description of control modes (Extended Control Mode and Non-Extended Control Mode), and features.
The ADC12D1x00 uses a calibrated folding and interpolating architecture that achieves a high Effective Number of Bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high-performance, low-power converter.
The analog input signal (which is within the converter's input voltage range) is digitized to twelve bits at speeds of 150/150 MSPS to 2.0/3.2 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of all ones. Either of these conditions at the I- or Q-input will cause the Out-of-Range I-channel or Q-channel output (ORI or ORQ), respectively, to output a logic-high signal.
In ECM, an expanded feature set is available through the Serial Interface. The ADC12D1x00 builds upon previous architectures, introducing a new DES Mode timing adjust feature, AutoSync feature for multi-chip synchronization and increasing to 15-bit for gain and 12-bit plus sign for offset the independent programmable adjustment for each channel.
Each channel has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demux Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demux Mode is selected, the output data rate on each channel is at the same rate as the input sample clock and only one 12-bit bus per channel is active.
The ADC12D1x00 offers many features to make the device convenient to use in a wide variety of applications. Table 1 is a summary of the features available, as well as details for the control mode chosen. "N/A" means "Not Applicable."
FEATURE | NON-ECM | CONTROL PIN
ACTIVE IN ECM |
ECM | DEFAULT ECM STATE |
---|---|---|---|---|
INPUT CONTROL AND ADJUST | ||||
AC-DC-coupled Mode Selection | Selected through VCMO
(Pin C2) |
Yes | Not available | N/A |
Input Full-scale Range Adjust | Selected through FSR (Pin Y3) |
No | Selected through the Config Reg (Addr: 3h and Bh) |
Mid FSR value |
Input Offset Adjust Setting | Not available | N/A | Selected through the Config Reg (Addr: 2h and Ah) |
Offset = 0 mV |
DES/Non-DES Mode Selection | Selected through DES (Pin V5) |
No | Selected through the DES Bit (Addr: 0h; Bit: 7) |
Non-DES Mode |
DES Timing Adjust | Not available | N/A | Selected through the DES Timing Adjust Reg (Addr: 7h) |
Mid skew offset |
Sampling Clock Phase Adjust | Not available | N/A | Selected through the Config Reg (Addr: Ch and Dh) |
tAD adjust disabled |
OUTPUT CONTROL AND ADJUST | ||||
DDR Clock Phase Selection | Selected through DDRPh (Pin W4) | No | Selected through the DPS Bit (Addr: 0h; Bit: 14) |
0° Mode |
LVDS Differential Voltage Amplitude Selection | Higher amplitude only | N/A | Selected through the OVS Bit (Addr: 0h; Bit: 13) |
Higher amplitude |
LVDS Common-Mode Voltage Amplitude Selection | Selected through VBG
(Pin B1) |
Yes | Not available | N/A |
Output Formatting Selection | Offset Binary only | N/A | Selected through the 2SC Bit (Addr: 0h; Bit: 4) |
Offset Binary |
Test Pattern Mode at Output | Selected through TPM (Pin A4) |
No | Selected through the TPM Bit (Addr: 0h; Bit: 12) |
TPM disabled |
Demux/Non-Demux Mode Selection | Selected through NDM (Pin A5) |
Yes | Not available | N/A |
AutoSync | Not available | N/A | Selected through the Config Reg (Addr: Eh) |
Master Mode, RCOut1/2 disabled |
DCLK Reset | Not available | N/A | Selected through the Config Reg (Addr: Eh; Bit: 0) |
DCLK Reset disabled |
Time Stamp | Not available | N/A | Selected through the TSE Bit (Addr: 0h; Bit: 3) |
Time Stamp disabled |
CALIBRATION | ||||
On-command Calibration | Selected through CAL (Pin D6) |
Yes | Selected through the CAL Bit (Addr: 0h; Bit: 15) |
N/A (CAL = 0) |
Power-on Calibration Delay Selection | Selected through CalDly (Pin V4) |
Yes | Not available | N/A |
Calibration Adjust | Not available | N/A | Selected through the Config Reg (Addr: 4h) |
tCAL |
Read/Write Calibration Settings | Not available | N/A | Selected through the SSC Bit (Addr: 4h; Bit: 7) |
R/W calibration values disabled |
POWER-DOWN | ||||
Power-down I-channel | Selected through PDI (Pin U3) |
Yes | Selected through the PDI Bit (Addr: 0h; Bit: 11) |
I-channel operational |
Power-down Q-channel | Selected through PDQ (Pin V3) |
Yes | Selected through the PDQ Bit (Addr: 0h; Bit: 10) |
Q-channel operational |
There are several features and configurations for the input of the ADC12D1x00 so that it may be used in many different applications. This section covers AC-DC-coupled Mode, input full-scale range adjust, input offset adjust, DES/Non-DES Mode, and sampling clock phase adjust.
The analog inputs may be AC or DC-coupled. SeeAC-DC-Coupled Mode Pin (VCMO) for information on how to select the desired mode and DC-Coupled Input Signals and AC-Coupled Input Signals for applications information.
The input full-scale range for the ADC12D1x00 may be adjusted through Non-ECM or ECM. In Non-ECM, a control pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale range may be adjusted with 15-bits of precision. See VIN_FSR in Electrical Characteristics: Analog Input/Output and Reference for electrical specification details. The higher and lower full-scale input range settings in Non-ECM correspond to the mid and min full-scale input range settings in ECM. It is necessary to execute an on-command calibration following a change of the input full-scale range. See Register Maps for information about the registers.
The input offset adjust for the ADC12D1x00 may be adjusted with 12-bits of precision plus sign through ECM. See Register Maps for information about the registers.
The performance of the ADC12D1x00 in DES Mode depends on how well the two channels are interleaved, that is, that the clock samples either channel with precisely a 50% duty-cycle, each channel has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1x00 includes an automatic clock phase background adjustment in DES Mode to automatically and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the residual fixed timing skew offset may be further manually adjusted, and further reduce timing spurs for specific applications. See the DES Timing Adjust (Addr: 7h). As the DES Timing Adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur will decrease to a local minimum and then increase again. The default, nominal setting of 64d may or may not coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving spur.
The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase array antennas.
Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust. Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in his system before relying on it.
There are several features and configurations for the output of the ADC12D1x00 so that it may be used in many different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage, output formatting, Demux/Non-demux Mode, Test Pattern Mode, and Time Stamp.
The ADC12D1x00 output data is always delivered in Double Data Rate (DDR). With DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 63. The DCLK-to-Data phase relationship may be either 0° or 90°. For 0° Mode, the Data transitions on each edge of the DCLK. Any offset from this timing is tOSK; see Electrical Characteristics: AC for details. For 90° Mode, the DCLK transitions in the middle of each Data cell. Setup and hold times for this transition, tSU and tH, may also be found in Electrical Characteristics: AC. The DCLK-to-Data phase relationship may be selected through the DDRPh Pin in Non-ECM (see Dual Data Rate Phase Pin (DDRPH)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.
The ADC12D1x00 is available with a selectable higher or lower LVDS output differential voltage. This parameter is VOD and may be found in Electrical Characteristics: Digital Control and Output Pin. The desired voltage may be selected through the OVS Bit (Addr: 0h, Bit 13). For many applications, in which the LVDS outputs are very close to an FPGA on the same board, for example, the lower setting is sufficient for good performance; this will also reduce the possibility for EMI from the LVDS outputs to other signals on the board. See Register Maps for more information.
The ADC12D1x00 is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is VOS and may be found in Electrical Characteristics: Digital Control and Output Pin. See LVDS Output Common-Mode Pin (VBG) for information on how to select the desired voltage.
The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting is offset binary, but two's complement may be selected through the 2SC Bit (Addr: 0h, Bit 4); see Register Maps for more information.
The ADC12D1x00 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is programmed into the Demux Mode, the test pattern’s order is described in Table 2. If the I- or Q-channel is powered down, the test pattern will not be output for that channel.
TIME | Qd | Id | Q | I | ORQ | ORI | COMMENTS |
---|---|---|---|---|---|---|---|
T0 | 000h | 004h | 008h | 010h | 0b | 0b | Pattern Sequence n |
T1 | FFFh | FFBh | FF7h | FEFh | 1b | 1b | |
T2 | 000h | 004h | 008h | 010h | 0b | 0b | |
T3 | FFFh | FFBh | FF7h | FEFh | 1b | 1b | |
T4 | 000h | 004h | 008h | 010h | 0b | 0b | |
T5 | 000h | 004h | 008h | 010h | 0b | 0b | Pattern Sequence n+1 |
T6 | FFFh | FFBh | FF7h | FEFh | 1b | 1b | |
T7 | 000h | 004h | 008h | 010h | 0b | 0b | |
T8 | FFFh | FFBh | FF7h | FEFh | 1b | 1b | |
T9 | 000h | 004h | 008h | 010h | 0b | 0b | |
T10 | 000h | 004h | 008h | 010h | 0b | 0b | Pattern Sequence n+2 |
T11 | FFFh | FFBh | FF7h | FEFh | 1b | 1b | |
T12 | 000h | 004h | 008h | 010h | 0b | 0b | |
T13 | ... | ... | ... | ... | ... | ... |
When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 3.
TIME | Q | I | ORQ | ORI | COMMENTS |
---|---|---|---|---|---|
T0 | 000h | 004h | 0b | 0b | Pattern Sequence n |
T1 | 000h | 004h | 0b | 0b | |
T2 | FFFh | FFBh | 1b | 1b | |
T3 | FFFh | FFBh | 1b | 1b | |
T4 | 000h | 004h | 0b | 0b | |
T5 | FFFh | FFBh | 1b | 1b | |
T6 | 000h | 004h | 0b | 0b | |
T7 | FFFh | FFBh | 1b | 1b | |
T8 | FFFh | FFBh | 1b | 1b | |
T9 | FFFh | FFBh | 1b | 1b | |
T10 | 000h | 004h | 0b | 0b | Pattern Sequence n+1 |
T11 | 000h | 004h | 0b | 0b | |
T12 | FFFh | FFBh | 1b | 1b | |
T13 | FFFh | FFBh | 1b | 1b | |
T14 | ... | ... | ... | ... |
The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal. When enabled through the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.
The ADC12D1x00 calibration must be run to achieve specified performance. The calibration procedure is exactly the same regardless of how it was initiated or when it is run. Calibration trims the analog input differential termination resistors, the CLK input resistor, and sets internal bias currents which affect the linearity of the converter. This minimizes full-scale error, offset error, DNL and INL, which results in the maximum dynamic performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB.
Table 4 is a summary of the pins and bits used for calibration. See Pin Configuration and Functions for complete pin information and Figure 6 for the timing diagram.
PIN (BIT) | NAME | FUNCTION |
---|---|---|
D6 (Addr: 0h; Bit 15) |
CAL (Calibration) |
Initiate calibration |
V4 | CalDly (Calibration Delay) |
Select power-on calibration delay |
(Addr: 4h) | Calibration Adjust | Adjust calibration sequence |
B5 | CalRun (Calibration Running) |
Indicates while calibration is running |
C1/D2 | Rtrim+/- (Input termination trim resistor) |
External resistor used to calibrate analog and CLK inputs |
C3/D3 | Rext+/- (External Reference resistor) |
External resistor used to calibrate internal linearity |
Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, and then holding it high for at least another tCAL_H clock cycles, as defined in Timing Requirements: Calibration. The minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as tCAL. The CAL Pin is active in both ECM and Non-ECM. However, in ECM, the CAL Pin is logically OR'd with the CAL Bit, so both the pin and bit are required to be set low before executing another calibration through either pin or bit.
For standard operation, power-on calibration begins after a time delay following the application of power, as determined by the setting of the CalDly Pin and measured by tCalDly (see Timing Requirements: Calibration). This delay allows the power supply to come up and stabilize before the power-on calibration takes place. The best setting (short or long) of the CalDly Pin depends upon the settling time of the power supply.
TI strongly recommends setting CalDly Pin (to either logic-high or logic-low) before powering the device on because this pin affects the power-on calibration timing. This may be accomplished by setting CalDly through an external 1-kΩ resistor connected to GND or VA. If the CalDly Pin is toggled while the device is powered on, it can execute a calibration even though the CAL Pin/Bit remains logic-low.
The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1x00 will function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired.
If it is necessary to toggle the CalDly Pin before the system power-up sequence, then the CAL Pin/Bit must be set to logic-high during the toggling and afterwards for 109 Sampling Clock cycles. This will prevent the power-on calibration, so an on-command calibration must be executed or the performance will be impaired.
In addition to the power-on calibration, TI recommends executing an on-command calibration whenever the settings or conditions to the device are altered significantly, to obtain optimal parametric performance. Some examples include: changing the FSR through either ECM or Non-ECM, power-cycling either channel, and switching into or out of DES Mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific system performance requirements.
Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the Serial Interface or use the DCLK Reset feature while calibrating the ADC. Doing so will impair the performance of the device until it is re-calibrated correctly. Also, TI recommends not applying a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.
The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration time than the default is required; see tCAL in Timing Requirements: Calibration. However, the performance of the device, when using this feature is not ensured.
The calibration sequence may be adjusted through CSS (Addr: 4h, Bit 14). The default setting of CSS = 1b executes both RIN and RIN_CLK Calibration (using Rtrim) and internal linearity Calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity Calibration. The first time that Calibration is executed, it must be with CSS = 1b to trim RIN and RIN_CLK. However, once the device is at its operating temperature and RIN has been trimmed at least one time, it will not drift significantly. To save time in subsequent calibrations, trimming RIN and RIN_CLK may be skipped, that is, by setting CSS = 0b.
When the ADC performs a calibration, the calibration constants are stored in an array which is accessible through the Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration, tCAL, or to allow re-use of a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, RIN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally determined by the ADC.
To read calibration values from the SPI, do the following:
To write calibration values to the SPI, do the following:
If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1x00 will immediately power down. The calibration cycle will continue when either or both channels are powered back up, but the calibration will be compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration should be executed upon powering the ADC12D1x00 back up. In general, the ADC12D1x00 should be recalibrated when either or both channels are powered back up, or after one channel is powered down. For best results, this should be done after the device has stabilized to its operating temperature.
During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-low, it takes an additional 60 Sampling Clock cycles before the output of the ADC12D1x00 is valid converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes.
On the ADC12D1x00, the I- and Q-channels may be powered down individually. This may be accomplished through the control pins, PDI and PDQ, or through ECM. In ECM, the PDI and PDQ pins are logically OR'd with the Control Register setting. See Power-Down I-Channel Pin (PDI) and Power-Down Q-Channel Pin (PDQ) for more information.
The ADC12D1x00 can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode allows for a single analog input to be sampled by both I- and Q-channels. One channel samples the input on the rising edge of the sampling clock and the other samples the same input signal on the falling edge of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the sampling clock frequency, for example, 2.0/3.2 GSPS with a 1.0/1.6 GHz sampling clock. Because DES Mode uses both I- and Q-channels to process the input signal, both channels must be powered up for the DES Mode to function properly.
In Non-ECM, only the I-input may be used for the DES Mode input. See Dual Edge Sampling Pin (DES) for information on how to select the DES Mode. In ECM, either the I- or Q-input may be selected by first using the DES bit (Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr: 0h, Bit: 6) is used to select the Q-input, but the I-input is used by default. Also, both I- and Q-inputs may be driven externally, that is, DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See Driving the ADC in DES Mode for more information about how to drive the ADC in DES Mode.
The DESIQ Mode results in the best DES Mode bandwidth. In general, the bandwidth decreases from Non-DES Mode to DES Mode (specifically, DESI or DESQ) because both channels are sampling off the same input signal and non-ideal effects introduced by interleaving the two channels lower the bandwidth. Driving both I- and Q-channels externally (DESIQ Mode) results in better bandwidth for the DES Mode because each channel is being driven, which reduces routing losses.
In the DES Mode, the outputs must be carefully interleaved to reconstruct the sampled signal. If the device is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If the sampling clock is 1.0/1.6 GHz, the effective sampling rate is doubled to 2.0/3.2 GSPS and each of the 4 output buses has an output rate of 500/800 MSPS. All data is available in parallel. To properly reconstruct the sampled waveform, the four bytes of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See Figure 3. If the device is programmed into the Non-Demux DES Mode, two bytes of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI. See Figure 4.
The ADC12D1x00 may be in one of two demultiplex modes: Demux Mode or Non-Demux Mode (also sometimes referred to as 1:1 Demux Mode). In Non-Demux Mode, the data from the input is simply output at the sampling rate on one 12-bit bus. In Demux Mode, the data from the input is output at half the sampling rate, on twice the number of buses. Demux/Non-Demux Mode may only be selected by the NDM pin. In Non-DES Mode, the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES Mode) or not demultiplexed (Non-Demux Non-DES Mode). In DES Mode, the output data from both channels interleaved may be demultiplexed (1:4 Demux DES Mode) or not demultiplexed (Non-Demux DES Mode).
The ADC12D1x00 may be operated in one of two control modes: Non-extended Control Mode (Non-ECM) or Extended Control Mode (ECM). In the simpler Non-ECM (also sometimes referred to as Pin Control Mode), the user affects available configuration and control of the device through the control pins. The ECM provides additional configuration and control options through a serial interface and a set of 16 registers, most of which are available to the customer.
In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are controlled through various pin settings. Non-ECM is selected by setting the ECE Pin to logic-high. For the control pins, "logic-high" and "logic-low" refer to VA and GND, respectively. Nine dedicated control pins provide a wide range of control for the ADC12D1x00 and facilitate its operation. These control pins provide DES Mode selection, Demux Mode selection, DDR Phase selection, execute Calibration, Calibration Delay setting, Power-down I-channel, Power-down Q-channel, Test Pattern Mode selection, and Full-Scale Input Range selection. In addition to this, two dual-purpose control pins provide for AC-DC-coupled Mode selection and LVDS output common-mode voltage selection. See Table 5 for a summary.
PIN NAME | LOGIC-LOW | LOGIC-HIGH | FLOATING |
---|---|---|---|
DEDICATED CONTROL PINS | |||
DES | Non-DES Mode | DES Mode |
Not valid |
NDM | Demux Mode |
Non-Demux Mode | Not valid |
DDRPh | 0° Mode | 90° Mode | Not valid |
CAL | See Calibration Pin (CAL) | Not valid | |
CalDly | Shorter delay | Longer delay | Not valid |
PDI | I-channel active | Power Down I-channel |
Power Down I-channel |
PDQ | Q-channel active | Power Down Q-channel |
Power Down Q-channel |
TPM | Non-Test Pattern Mode | Test Pattern Mode | Not valid |
FSR | Lower FS input Range | Higher FS input Range | Not valid |
DUAL-PURPOSE CONTROL PINS | |||
VCMO | AC-coupled operation | Not allowed | DC-coupled operation |
VBG | Not allowed | Higher LVDS common-mode voltage | Lower LVDS common-mode voltage |
The Dual Edge Sampling (DES) Pin selects whether the ADC12D1x00 is in DES Mode (logic-high) or Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a time-interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In Non-ECM, only the I-input may be used for DES Mode, a.k.a. DESI Mode. In ECM, the Q-input may be selected through the DEQ Bit (Addr: 0h, Bit: 6), a.k.a. DESQ Mode. In ECM, both the I- and Q-inputs may be selected, a.k.a. DESIQ Mode.
To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES Mode for more information.
The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1x00 is in Demux Mode (logic-low) or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the sampled rate at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the sampled rate at twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce its data on one or two buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected channel will produce its data on two or four buses for Non-Demux or Demux Mode, respectively.
This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Demux/Non-Demux Mode for more information.
The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1x00 is in 0° Mode (logic-low) or 90° Mode (logic-high). The Data is always produced in DDR Mode on the ADC12D1x00. The Data may transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode). The DDRPh Pin selects 0° Mode or 90° Mode for both the I-channel: DI- and DId-to-DCLKI phase relationship and for the Q-channel: DQ- and DQd-to-DCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See DDR Clock Phase for more information.
The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration through the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power-on will prevent execution of the power-on calibration. In ECM, this pin remains active and is logically OR'd with the CAL bit.
To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration Feature for more information.
The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the application of power, until the start of the power-on calibration. The actual delay time is specified as tCalDly and may be found in Timing Requirements: Calibration. This feature is pin-controlled only and remains active in ECM. TI recommends selecting the desired delay time before power-on and not dynamically alter this selection.
See Calibration Feature for more information.
The Power-Down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active (logic-low). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will contain meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I-channel powered down or active and may be found in Electrical Characteristics: Power Supply. The device should be recalibrated following a power-cycle of PDI (or PDQ).
This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used to power-down the I-channel. See Power Down for more information.
The Power-Down Q-channel (PDQ) Pin selects whether the Q-channel is powered down (logic-high) or active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q-channel. The PDI and PDQ pins function independently of each other to control whether each I- or Q-channel is powered down or active.
This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be used to power-down the Q-channel. See Power Down for more information.
The Test Pattern Mode (TPM) Pin selects whether the output of the ADC12D1x00 is a test pattern (logic-high) or the converted analog input (logic-low). The ADC12D1x00 can provide a test pattern at the four output buses independently of the input signal to aid in system debug. In TPM, the ADC is disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. See Test Pattern Mode for more information.
The Full-Scale Input Range (FSR) Pin selects whether the full-scale input range for both the I- and Q-channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in Electrical Characteristics: Analog Input/Output and Reference. In Non-ECM, the full-scale input range for each I- and Q-channel may not be set independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to obtain optimal performance.
To use this feature in ECM, use the Configuration Registers (Addr: 3h and Bh). See Input Control and Adjust for more information.
The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and Non-ECM.
The VBG Pin serves a dual purpose. When functioning as an output, it provides the bandgap reference. When functioning as an input, it selects whether the LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be found in Electrical Characteristics: Digital Control and Output Pin. This pin is always active, in both ECM and Non-ECM.
In Extended Control Mode (ECM), most functions are controlled through the Serial Interface. In addition to this, several of the control pins remain active. See Table 1 for details. ECM is selected by setting the ECE Pin to logic-low. If the ECE Pin is set to logic-high (Non-ECM), then the registers are reset to their default values. So, a simple way to reset the registers is by toggling the ECE pin. Four pins on the ADC12D1x00 control the Serial Interface: SCS, SCLK, SDI and SDO. This section covers the Serial Interface. The Register Definitions are located at the end of the data sheet so that they are easy to find, see Register Maps.
The ADC12D1x00 offers a Serial Interface that allows access to the sixteen control registers within the device. The Serial Interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in his system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 6. See Figure 7 for the timing diagram and Timing Requirements: Serial Port Interface for timing specification details. Control register contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and SCS pins may be left floating because they each have an internal pullup.
PIN | NAME |
---|---|
C4 | SCS (Serial Chip Select bar) |
C5 | SCLK (Serial Clock) |
B4 | SDI (Serial Data In) |
A3 | SDO (Serial Data Out) |
SCS: Each assertion (logic-low) of this signal starts a new register access, that is, the SDI command field must be ready on the following SCLK rising edge. The user is required to deassert this signal after the 24th clock. If the SCS is deasserted before the 24th clock, no data read/write will occur. For a read operation, if the SCS is asserted longer than 24 clocks, the SDO output will hold the D0 bit until SCS is deasserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write will occur normally through the SDI input upon the 24th clock. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed. SCS must be toggled in between register access cycles.
SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see fSCLK in Timing Requirements: Serial Port Interface for more details.
SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. If the SDI and SDO wires are shared (3-wire mode), then during read operations, it is necessary to tri-state the master which is driving SDI while the data field is being output by the ADC on SDO. The master must be at TRI-STATE before the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed.
SDO: This output is normally at TRI-STATE and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th clock's falling edge. At the end of the access, when SCS is deasserted, this output is at TRI-STATE once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there will be a bus turnaround time, tBSU, from when the last bit of the command field was read in until the first bit of the data field is written out.
Table 7 shows the Serial Interface bit definitions.
BIT NO. | NAME | COMMENTS |
---|---|---|
1 | Read/Write (R/W) | 1b indicates a read operation 0b indicates a write operation |
2-3 | Reserved | Bits must be set to 10b |
4-7 | A<3:0> | 16 registers may be addressed. The order is MSB first |
8 | X | This is a "don't care" bit |
9-24 | D<15:0> | Data written to or read from addressed register |
The serial data protocol is shown for a read and write operation in Figure 64 and Figure 65, respectively.
Ten read/write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. See Table 8 for a summary. For a description of the functionality and timing to read/write the control registers, see The Serial Interface.
A3 | A2 | A1 | A0 | Hex | Register Addressed |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0h | Configuration Register 1 |
0 | 0 | 0 | 1 | 1h | Reserved |
0 | 0 | 1 | 0 | 2h | I-channel Offset |
0 | 0 | 1 | 1 | 3h | I-channel Full-Scale Range |
0 | 1 | 0 | 0 | 4h | Calibration Adjust |
0 | 1 | 0 | 1 | 5h | Calibration Values |
0 | 1 | 1 | 0 | 6h | Reserved |
0 | 1 | 1 | 1 | 7h | DES Timing Adjust |
1 | 0 | 0 | 0 | 8h | Reserved |
1 | 0 | 0 | 1 | 9h | Reserved |
1 | 0 | 1 | 0 | Ah | Q-channel Offset |
1 | 0 | 1 | 1 | Bh | Q-channel Full-Scale Range |
1 | 1 | 0 | 0 | Ch | Aperture Delay Coarse Adjust |
1 | 1 | 0 | 1 | Dh | Aperture Delay Fine Adjust |
1 | 1 | 1 | 0 | Eh | AutoSync |
1 | 1 | 1 | 1 | Fh | Reserved |
Addr: 0h (0000b) | POR state: 2000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | CAL | DPS | OVS | TPM | PDI | PDQ | Res | LFS | DES | DEQ | DIQ | 2SC | TSE | Res | ||
POR | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 | CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration. |
Bit 14 | DPS: DCLK Phase Select. In DDR, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the 90° Mode. If the device is in Non-Demux Mode, this bit has no effect; the device will always be in 0°DDR Mode. |
Bit 13 | OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Electrical Characteristics: Digital Control and Output Pin for details. |
Bit 12 | TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog inputs. See Test Pattern Mode for details about the TPM pattern. |
Bit 11 | PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is powered-down. The I-channel may be powered-down through this bit or the PDI Pin, which is active, even in ECM. |
Bit 10 | PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel is powered-down. The Q-channel may be powered-down through this bit or the PDQ Pin, which is active, even in ECM. |
Bit 9 | Reserved. Must be set to 0b. |
Bit 8 | LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1b for improved performance. |
Bit 7 | DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set to 1b, the device will operate in the DES Mode. See DES/Non-DES Mode for more information. |
Bit 6 | DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the device will operate on. The default setting of 0b selects the I-input and 1b selects the Q-input. |
Bit 5 | DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1b shorts the I- and Q-inputs internally to the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. To operate the device in DESIQ Mode, Bits<7:5> must be set to 101b. In this mode, both the I- and Q-inputs must be externally driven; see DES/Non-DES Mode for more information. |
Bit 4 | 2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set to 1b, the data is output in Two's Complement format. |
Bit 3 | TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the feature is enabled. See Output Control and Adjust for more information about this feature. |
Bits 2:0 | Reserved. Must be set as shown. |
Addr: 1h (0001b) | POR state: 2A0Eh | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | |||||||||||||||
POR | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
Bits 15:0 | Reserved. Must be set as shown. |
Addr: 2h (0010b) | POR state: 0000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | OS | OM(11:0) | |||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:13 | Reserved. Must be set to 0b. | |
Bit 12 | OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bet to 1b incurs a negative offset of the set magnitude. | |
Bits 11:0 | OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of approximately 11 µV. Monotonicity is ensured by design only for the 9 MSBs. | |
Code | Offset [mV] | |
0000 0000 0000 (default) | 0 | |
1000 0000 0000 | 22.5 | |
1111 1111 1111 | 45 |
Addr: 3h (0011b) | POR state: 4000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | FM(14:0) | ||||||||||||||
POR | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 | Reserved. Must be set to 0b. | |
Bits 14:0 | FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is ensured by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Electrical Characteristics: Analog Input/Output and Reference for characterization details. | |
Code | FSR [mV] | |
000 0000 0000 0000 | 600 | |
100 0000 0000 0000 (default) | 800 | |
111 1111 1111 1111 | 1000 |
Addr: 4h (0100b) | POR state: DF4Bh | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | CSS | Res | SSC | Res | |||||||||||
POR | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
Bit 15 | Reserved. Must be set as shown. |
Bit 14 | CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity Calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity Calibration). |
Bits 13:8 | Reserved. Must be set as shown. |
Bit 7 | SSC: SPI Scan Control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read/written. When not reading/writing the calibration values, this control bit should left at its default 0b setting. See Calibration Feature for more information. |
Bits 6:0 | Reserved. Must be set as shown. |
Addr: 5h (0101b) | POR state: XXXXh | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | SS(15:0) | |||||||||||||||
POR | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Bits 15:0 | SS(15:0): SPI Scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may be read from/ written to it. Set SSC (Addr: 4h, Bit 7) to read/write. See Calibration Feature for more information. |
Addr: 6h (0110b) | POR state: 1C20h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | |||||||||||||||
POR | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bits 15:0 | Reserved. Must be set as shown. |
Addr: 7h (0111b) | POR state: 8140h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | DTA(6:0) | Res | ||||||||||||||
POR | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:9 | DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input Control and Adjust for more information. The nominal step size is 30fs. |
Bits 8:0 | Reserved. Must be set as shown. |
Addr: 8h (1000b) | POR state: 0000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | |||||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:0 | Reserved. Must be set as shown. |
Addr: 9h (1001b) | POR state: 0000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | |||||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:0 | Reserved. Must be set as shown. |
Addr: Ah (1010b) | POR state: 0000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | OS | OM(11:0) | |||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:13 | Reserved. Must be set to 0b. | |
Bit 12 | OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bet to 1b incurs a negative offset of the set magnitude. | |
Bits 11:0 | OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of approximately 11 µV. Monotonicity is ensured by design only for the 9 MSBs. | |
Code | Offset [mV] | |
0000 0000 0000 (default) | 0 | |
1000 0000 0000 | 22.5 | |
1111 1111 1111 | 45 |
Addr: Bh (1011b) | POR state: 4000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | FM(14:0) | ||||||||||||||
POR | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 | Reserved. Must be set to 0b. | |
Bits 14:0 | FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is ensured by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Electrical Characteristics: Analog Input/Output and Reference for characterization details. | |
Code | FSR [mV] | |
000 0000 0000 0000 | 600 | |
100 0000 0000 0000 (default) | 800 | |
111 1111 1111 1111 | 1000 |
Addr: Ch (1100b) | POR state: 0004h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | CAM(11:0) | STA | DCC | Res | ||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Bits 15:4 | CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of approximately 340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function. |
Bit 3 | STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which will make both coarse and fine adjustment settings, that is, CAM(11:0) and FAM(5:0), available. |
Bit 2 | DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature is enabled by default. |
Bits 1:0 | Reserved. Must be set to 0b. |
Addr: Dh (1101b) | POR state: 0000h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | FAM(5:0) | Res | Res | |||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:10 | FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to the input CLK when the Clock Phase Adjust feature is enabled through STA (Addr: Ch, Bit 3). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of approximately 36 fs. |
Bits 9:0 | Reserved. Must be set as shown. |
Addr: Eh (1110b) | POR state: 0003h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | DRC(8:0) | Res | SP(1:0) | ES | DOC | DR | ||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
Bits 15:7 | DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference clock when synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1000 ps (319d). The delay remains the maximum of 1000 ps for any codes above or equal to 319d. See Synchronizing Multiple ADC12D1x00s in a System for more information. |
Bits 6:5 | Reserved. Must be set as shown. |
Bits 4:3 | SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the following phase shift: 00 = 0° 01 = 90° 10 = 180° 11 = 270° |
Bit 2 | ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this bit is set to 0b, then the device is in Master Mode. |
Bit 1 | DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in Master or Slave Mode, as determined by ES (Bit 2). |
Bit 0 | DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality. |
Addr: Fh (1111b) | POR state: 0018h | |||||||||||||||
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Name | Res | |||||||||||||||
POR | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
Bits 15:0 | Reserved. This address is read only. |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ADC12D1x00 will continuously convert any signal which is present at the analog inputs, as long as a CLK signal is also provided to the device. This section covers important aspects related to the analog inputs including: acquiring the input, driving the ADC in DES Mode, the reference voltage and FSR, out-of-range indication, AC-DC-coupled signals, and single-ended input signals.
Data is acquired at the rising edge of CLK+ in Non-DES Mode and both the falling and rising edges of CLK+ in DES Mode. The digital equivalent of that data is available at the digital outputs a constant number of sampling clock cycles later for the DI, DQ, DId and DQd output buses, a.k.a. Latency, depending on the demultiplex mode which is selected. See tLAT in Electrical Characteristics: AC. In addition to the Latency, there is a constant output delay, tOD, before the data is available at the outputs. See tOD in Electrical Characteristics: AC and the timing diagrams.
The output latency versus Demux/Non-Demux Mode is shown in Table 25 and Table 26, respectively. For DES Mode, the I- and Q-channel inputs are available in ECM, but only the I-channel input is available in Non-ECM.
DATA | NON-DES MODE | DES MODE | |
---|---|---|---|
Q-INPUT(1) | I-INPUT | ||
DI | I-input sampled with rise of CLK, 34 cycles earlier |
Q-input sampled with rise of CLK, 34 cycles earlier |
I-input sampled with rise of CLK, 34 cycles earlier |
DQ | Q-input sampled with rise of CLK, 34 cycles earlier |
Q-input sampled with fall of CLK, 34.5 cycles earlier |
I-input sampled with fall of CLK, 34.5 cycles earlier |
DId | I-input sampled with rise of CLK, 35 cycles earlier |
Q-input sampled with rise of CLK, 35 cycles earlier |
I-input sampled with rise of CLK, 35 cycles earlier |
DQd | Q-input sampled with rise of CLK, 35 cycles earlier |
Q-input sampled with fall of CLK, 35.5 cycles earlier |
I-input sampled with fall of CLK, 35.5 cycles earlier |
DATA | NON-DES MODE | DES MODE | |
---|---|---|---|
Q-INPUT(1) | I-INPUT | ||
DI | I-input sampled with rise of CLK, 34 cycles earlier |
Q-input sampled with rise of CLK, 34 cycles earlier |
I-input sampled with rise of CLK, 34 cycles earlier |
DQ | Q-input sampled with rise of CLK, 34 cycles earlier |
Q-input sampled with rise of CLK, 34.5 cycles earlier |
I-input sampled with rise of CLK, 34.5 cycles earlier |
DId | No output; high impedance. |
||
DQd | No output; high impedance. |
The ADC12D1x00 can be configured as either a 2-channel, 1.0/1.6 GSPS device (Non-DES Mode) or a 1-channel 2.0/3.2 GSPS device (DES Mode). When the device is configured in DES Mode, there is a choice for with which input to drive the single-channel ADC. These are the 3 options:
DES – externally driving the I-channel input only. This is the default selection when the ADC is configured in DES Mode. It may also be referred to as “DESI” for added clarity.
DESQ – externally driving the Q-channel input only.
DESIQ – externally driving both the I- and Q-channel inputs. VinI+ and VinQ+ should be driven with the exact same signal. VinI- and VinQ- should be driven with the exact same signal, which is the differential complement to the one driving VinI+ and VinQ+.
The input impedance for each I- and Q-input is 100 Ω differential (or 50 Ω single-ended), so the trace to each VinI+, VinI-, VinQ+, and VinQ- should always be 50 Ω single-ended. If a single I- or Q-input is being driven, then that input will present a 100-Ω differential load. For example, if a 50-Ω single-ended source is driving the ADC, then a 1:2 balun will transform the impedance to 100 Ω differential. However, if the ADC is being driven in DESIQ Mode, then the 100-Ω differential impedance from the I-input will appear in parallel with the Q-input for a composite load of 50 Ω differential and a 1:1 balun would be appropriate. See Figure 66 for an example circuit driving the ADC in DESIQ Mode. A recommended part selection is using the Mini-Circuits TC1-1-13MA+ balun with Ccouple = 0.22 µF.
In the case that only one channel is used in Non-DES Mode or that the ADC is driven in DESI or DESQ Mode, the unused analog input should be terminated to reduce any noise coupling into the ADC. See Table 27 for details.
MODE | POWER DOWN | COUPLING | RECOMMENDED TERMINATION |
---|---|---|---|
Non-DES | Yes | AC-DC | Tie Unused+ and Unused- to Vbg |
DES/Non-DES | No | DC | Tie Unused+ and Unused- to Vbg |
DES/Non-DES | No | AC | Tie Unused+ to Unused- |
The full-scale analog differential input range (VIN_FSR) of the ADC12D1x00 is derived from an internal bandgap reference. In Non-ECM, this full-scale range has two settings controlled by the FSR Pin; see Full-Scale Input Range Pin (FSR). The FSR Pin operates on both I- and Q-channels. In ECM, the full-scale range may be independently set for each channel through Addr:3h and Bh with 15 bits of precision; see Register Maps. The best SNR is obtained with a higher full-scale input range, but better distortion and SFDR are obtained with a lower full-scale input range. It is not possible to use an external analog reference voltage to modify the full-scale range, and this adjustment should only be done digitally, as described.
A buffered version of the internal bandgap reference voltage is made available at the VBG Pin for the user. The VBG pin can drive a load of up to 80 pF and source or sink up to 100 μA. It should be buffered if more current than this is required. This pin remains as a constant reference voltage regardless of what full-scale range is selected and may be used for a system reference. VBG is a dual-purpose pin and it may also be used to select a higher LVDS output common-mode voltage; see LVDS Output Common-Mode Pin (VBG).
Differential input signals are digitized to 12 bits, based on the full-scale range. Signal excursions beyond the full-scale range, that is, greater than +VIN_FSR/2 or less than -VIN_FSR/2, will be clipped at the output. An input signal which is above the FSR will result in all 1's at the output and an input signal which is below the FSR will result in all 0's at the output. When the conversion result is clipped for the I-channel input, the Out-of-Range I-channel (ORI) output is activated such that ORI+ goes high and ORI- goes low while the signal is out of range. This output is active as long as accurate data on either or both of the buses would be outside the range of 000h to FFFh. The Q-channel has a separate ORQ which functions similarly.
The recommended operating and absolute maximum input range may be found in Recommended Operating Conditions and Absolute Maximum Ratings, respectively. Under the stated allowed operating conditions, each Vin+ and Vin- input pin may be operated in the range from 0 V to 2.15 V if the input is a continuous 100% duty cycle signal and from 0 V to 2.5 V if the input is a 10% duty cycle signal. The absolute maximum input range for Vin+ and Vin- is from –0.15 V to 2.5 V. These limits apply only for input signals for which the input common-mode voltage is properly maintained.
The ADC12D1x00 analog inputs require a precise common-mode voltage. This voltage is generated on-chip when AC-coupling Mode is selected. See AC-DC-Coupled Mode Pin (VCMO) for more information about how to select AC-coupled Mode.
In AC-coupled Mode, the analog inputs must of course be AC-coupled. For an ADC12D1x00 used in a typical application, this may be accomplished by on-board capacitors, as shown in Figure 67. For the ADC12D1x00RB, the SMA inputs on the Reference Board are directly connected to the analog inputs on the ADC12D1x00, so this may be accomplished by DC blocks (included with the hardware kit).
When the AC-coupled Mode is selected, an analog input channel that is not used (for example, in DES Mode) should be connected to AC ground, for example, through capacitors to ground. Do not connect an unused analog input directly to ground.
The analog inputs for the ADC12D1x00 are internally buffered, which simplifies the task of driving these inputs and the RC pole which is generally used at sampling ADC inputs is not required. If the user desires to place an amplifier circuit before the ADC, care should be taken to choose an amplifier with adequate noise and distortion performance, and adequate gain at the frequencies used for the application.
In DC-coupled Mode, the ADC12D1x00 differential inputs must have the correct common-mode voltage. This voltage is provided by the device itself at the VCMO output pin. TI recommends using this voltage because the VCMO output potential will change with temperature and the common-mode voltage of the driving device should track this change. Full-scale distortion performance falls off as the input common mode voltage deviates from VCMO. Therefore, TI recommends keeping the input common-mode voltage within 100 mV of VCMO (typical), although this range may be extended to ±150 mV (maximum). See VCMI in Electrical Characteristics: Analog Input/Output and Reference and ENOB vs. VCMI in Typical Characteristics. Performance in AC- and DC-coupled Mode are similar, provided that the input common mode voltage at both analog inputs remains within 100 mV of VCMO.
The analog inputs of the ADC12D1x00 are not designed to accept single-ended signals. The best way to handle single-ended signals is to first convert them to differential signals before presenting them to the ADC. The easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-transformer, as shown in Figure 68.
When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of the analog source should be matched to the on-chip 100-Ω differential input termination resistor of the ADC12D1x00. The range of this termination resistor is specified as RIN in Electrical Characteristics: Analog Input/Output and Reference.
The ADC12D1x00 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-coupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100Ω differential and self-biased. This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.
The clock inputs of the ADC12D1x00 must be capacitively coupled to the clock pins as indicated in Figure 69.
The choice of capacitor value will depend on the clock frequency, capacitor component characteristics and other system economic factors. For example, on the ADC12D1x00RB, the capacitors have the value Ccouple = 4.7 nF which yields a highpass cutoff frequency, fc = 677.2 kHz.
Although the ADC12D1x00 is tested and its performance is ensured with a differential 1.0/1.6 GHz sampling clock, it will typically function well over the input clock frequency range; see fCLK(min) and fCLK(max) in Electrical Characteristics: AC. Operation up to fCLK(max) is possible if the maximum ambient temperatures indicated are not exceeded. Operating at sample rates above fCLK(max) for the maximum ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that higher sample rates results in higher power consumption and die temperatures. If fCLK < 300 MHz, enable LFS in the Control Register (Addr: 0h, Bit 8).
The input clock amplitude is specified as VIN_CLK in Electrical Characteristics: Converter and Sampling Clock. Input clock amplitudes above the max VIN_CLK may result in increased input offset voltage. This would cause the converter to produce an output code other than the expected 2047/2048 when both input pins are at the same potential. Insufficient input clock levels will result in poor dynamic performance. Both of these results may be avoided by keeping the clock input amplitude within the specified limits of VIN_CLK.
The duty cycle of the input clock signal can affect the performance of any A/D converter. The ADC12D1x00 features a duty cycle clock correction circuit which can maintain performance over the 20%-to-80% specified clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the Dual-Edge Sampling (DES) Mode.
High speed, high performance ADCs such as the ADC12D1x00 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be:
where
tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: the ADC input clock, system, input signals and the ADC itself. Because the effective jitter added by the ADC is beyond user control, TI recommends keeping the sum of all other externally added jitter to a minimum.
The ADC12D1x00 clock input is internally terminated with a trimmed 100-Ω resistor. The differential input clock line pair should have a characteristic impedance of 100 Ω and (when using a balun), be terminated at the clock source in that (100 Ω) characteristic impedance.
It is a good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well away from any other signals, and treat it as a transmission line. Otherwise, other signals can introduce jitter into the input clock signal. Also, the clock signal can introduce noise into the analog path if it is not properly isolated.
The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs are compatible with typical LVDS receivers available on ASIC and FPGA chips; but they are not IEEE or ANSI communications standards compliant due to the low 1.9-V supply used on this chip. These outputs should be terminated with a 100-Ω differential resistor placed as closely to the receiver as possible. If the 100-Ω differential resistance is built in to the receiver, then an externally placed resistor is not necessary. This section covers common-mode and differential voltage, and data rate.
The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Electrical Characteristics: Digital Control and Output Pin. See Output Control and Adjust for more information.
Selecting the higher VOS will also increase VOD slightly. The differential voltage, VOD, may be selected for the higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be realized with the lower VOD. This will also result in lower power consumption. If the LVDS lines are long and/or the system in which the ADC12D1x00 is used is noisy, it may be necessary to select the higher VOD.
The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input clock rate for this device is fCLK(MIN); see Electrical Characteristics: AC. However, it is possible to operate the device in 1:2 Demux Mode and capture data from just one 12-bit bus, for example, just DI (or DId) although both DI and DId are fully operational. This will decimate the data by two and effectively halve the data rate.
If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present on them. The DId and DQd data outputs may be left not connected; if unused, they are internally at TRI-STATE.
Similarly, if the Q-channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ and ORQ may be left not connected.
The ADC12D1x00 has two features to assist the user with synchronizing multiple ADCs in a system; AutoSync and DCLK Reset. The AutoSync feature is new and designates one ADC12D1x00 as the Master ADC and other ADC12D1x00s in the system as Slave ADCs. The DCLK Reset feature performs the same function as the AutoSync feature, but is the first generation solution to synchronizing multiple ADCs in a system; it is disabled by default. For the application in which there are multiple Master and Slave ADC12D1x00s in a system, AutoSync may be used to synchronize the Slave ADC12D1x00(s) to each respective Master ADC12D1x00 and the DCLK Reset may be used to synchronize the Master ADC12D1x00s to each other.
If the AutoSync or DCLK Reset feature is not used, see Table 28 for recommendations about terminating unused pins.
PINS | UNUSED TERMINATION |
---|---|
RCLK+/- | Do not connect. |
RCOUT1+/- | Do not connect. |
RCOUT2+/- | Do not connect. |
DCLK_RST+ | Connect to GND through 1-kΩ resistor. |
DCLK_RST- | Connect to VA through 1-kΩ resistor. |
AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1x00s in a system. It may be used to synchronize the DCLK and data outputs of one or more Slave ADC12D1x00s to one Master ADC12D1x00. Several advantages of this feature include: no special synchronization pulse required, any upset in synchronization is recovered upon the next DCLK cycle, and the Master/Slave ADC12D1x00s may be arranged as a binary tree so that any upset will quickly propagate out of the system.
An example system is shown below in Figure 70 which consists of one Master ADC and two Slave ADCs. For simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one another.
To synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some latency, plus tOD minus tAD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the tAD adjust feature may be used. However, using the tAD adjust feature will also affect when the DCLK is produced at the output. If the device is in Demux Mode, then there are four possible phases which each DCLK may be generated on because the typical CLK = 1 GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of the DCLK, so that each Slave DCLK is on the same phase as the Master DCLK.
The AutoSync feature may only be used through the Control Registers. For more information, see AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (SNAA073).
The DCLK reset feature is available through ECM, but it is disabled by default. DCLKI and DCLKQ are always synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.
The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 5 of the Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must observe setup and hold times with respect to the CLK input rising edge. These timing specifications are listed as tPWR, tSR and tHR and may be found in Electrical Characteristics: AC.
The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK continues to function normally. Depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is deasserted, there are tSYNC_DLY CLK cycles of systematic delay and the next CLK rising edge synchronizes the DCLK output with those of other ADC12D1x00s in the system. For 90° Mode (DDRPh = logic-high), the synchronizing edge occurs on the rising edge of CLK, 4 cycles after the first rising edge of CLK after DCLK_RST is released. For 0° Mode (DDRPh = logic-low), this is 5 cycles instead. The DCLK output is enabled again after a constant delay of tOD.
For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the reset state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK will come out of the reset state in a known way. Therefore, if using the DCLK Reset feature, TI recommends applying one "dummy" DCLK_RST pulse before using the second DCLK_RST pulse to synchronize the outputs. This recommendation applies each time the device or channel is powered-on.
When using DCLK_RST to synchronize multiple ADC12D1x00s, it is required that the Select Phase bits in the Control Register (Addr: Eh, Bits 3,4) be the same for each Master ADC12D1x00.
TI recommends these other chips including temperature sensors, clocking devices, and amplifiers to support the ADC12D1x00 in a system design.
The ADC12D1x00 has an on-die temperature diode connected to pins Tdiode+/- which may be used to monitor the die temperature. TI also provides a family of temperature sensors for this application which monitor different numbers of external devices, see Table 29.
NUMBER OF EXTERNAL DEVICES MONITORED | RECOMMENDED TEMPERATURE SENSOR |
---|---|
1 | LM95235 |
2 | LM95213 |
4 | LM95214 |
The temperature sensor (LM95235/13/14) is an 11-bit digital temperature sensor with a 2-wire System Management Bus (SMBus) interface that can monitor the temperature of one, two, or four remote diodes as well as its own temperature. It can be used to accurately monitor the temperature of up to one, two, or four external devices such as the ADC12D1x00, a FPGA, other system components, and the ambient temperature.
The temperature sensor reports temperature in two different formats for +127.875°C/-128°C range and 0°/255°C range. It has a Sigma-Delta ADC core which provides the first level of noise immunity. For improved performance in a noisy environment, the temperature sensor includes programmable digital filters for Remote Diode temperature readings. When the digital filters are invoked, the resolution for the Remote Diode readings increases to 0.03125°C. For maximum flexibility and best accuracy, the temperature sensor includes offset registers that allow calibration for other types of diodes.
Diode fault detection circuitry in the temperature sensor can detect the absence or fault state of a remote diode: whether D+ is shorted to the power supply, D- or ground, or floating.
In the following typical application, the LM95213 is used to monitor the temperature of an ADC12D1x00 as well as an FPGA, see Figure 71. If this feature is unused, the Tdiode+/- pins may be left floating.
The clock source can be a PLL or VCO device such as the LMX2531LQxxxx family of products. The specific device should be selected according to the desired ADC sampling clock frequency. The ADC12D1x00RB uses the LMX2531LQ1910E/1570E, with the ADC clock source provided by the Aux PLL output. Other devices which may be considered based on clock source, jitter cleaning, and distribution purposes are the LMK01XXX, LMK02XXX, LMK03XXX and LMK04XXX product families.
The following amplifiers can be used for ADC12D1x00 applications which require DC coupled input or signal gain, neither of which can be provided with a transformer coupled input circuit. In addition, several of the amplifiers provide single-ended to differential conversion options:
AMPLIFIER | BANDWIDTH | BRIEF FEATURES |
---|---|---|
LMH3401 | 7 GHz | Fixed gain, single-ended to differential conversion |
LMH5401 | 8 GHz | Configurable gain, single-ended to differential conversion |
LMH6401 | 4.5 GHz | Digital variable controlled gain |
LMH6554 | 2.8 GHz | Configurable gain |
LMH6555 | 1.2 GHz | Fixed gain |
The following baluns are recommended for the ADC12D1x00 for applications which require no gain. When evaluating a balun for the application of driving an ADC, some important qualities to consider are phase error and magnitude error.
BALUN | BANDWIDTH |
---|---|
Mini Circuits TC1-1-13MA+ | 4.5 - 3000MHz |
Anaren B0430J50100A00 | 400 - 3000 MHz |
Mini Circuits ADTL2-18 | 30 - 1800 MHz |
The ADC12D1600 can be used to directly sample a signal in the radio frequency range for downstream processing. The wide input bandwidth, buffered input, and high sampling rate make ADC12D1600 ideal for RF sampling applications.
In this example, ADC12D1600 will be used to sample signals in DES mode and Non-DES mode. The design parameters are listed in Table 32.
DESIGN PARAMETERS | EXAMPLE VALUES (Non-DES mode) | EXAMPLE VALUES (DES mode) |
---|---|---|
Signal center frequency | 1800 MHz | 1000 MHz |
Signal bandwidth | 100 MHz | 75 MHz |
ADC sampling Rate | 1600 MSPS | 3200 MSPS |
Signal nominal amplitude | –7 dBm | –7 dBm |
Signal maximum amplitude | 6 dBm | 6 dBm |
Minimum SNR (in BW of interest) | 48 dBc | 48 dBc |
Minimum THD (in BW of interest) | –57 dBc | –55 dBc |
Minimum SFDR (in BW of interest) | 53 dBc | 50 dBc |
Use the step described below to design the RF receiver:
Figure 73 and Figure 74 show an RF signal at 1797.97 MHz captured at a sample rate of 1600 MSPS in Non-DES mode and an RF signal at 997.97 MHz sample at an effective sample rate of 3200 MSPS in DES mode.
Non-DES Mode | |
Fin 1797.97 MHz at –7 dBFS | Fs = 1600 MHz |
DES Mode | |
Fin 997.97 MHz at –7 dBFS | Fs = 3200 MHz |
PARAMETER | VALUE |
---|---|
SNR | 49.7 dBc |
SFDR | 58.3 dBc |
THD | –64.4 dBc |
SINAD | 49.6 dBc |
ENOB | 7.9 bits |
PARAMETER | VALUE |
---|---|
SNR | 49.3 dBc |
SFDR | 53.6 dBc |
THD | –63.8 dBc |
SINAD | 49.2 dBc |
ENOB | 7.8 bits |