SNAS518J July   2011  – July 2015 ADC12D1800RF

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 4.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 4.7  Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics
    8. 4.8  Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics
    9. 4.9  Converter Electrical Characteristics: Sampling Clock Characteristics
    10. 4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics
    11. 4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 4.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 4.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 4.14 Converter Electrical Characteristics: Serial Port Interface
    15. 4.15 Converter Electrical Characteristics Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
      1. 5.1.1 RF Performance
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC/DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read / Write Calibration Settings
        7. 5.3.3.7 Calibration and Power-Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES/Non-DES Mode
      2. 5.4.2 Demux/Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC / DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
      1. 5.6.1 Register Definitions
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 LVDS Outputs
        1. 6.1.3.1 Common-mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1800RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 RF Sampling Receiver
      2. 6.2.2 Design Requirements
      3. 6.2.3 Detailed Design Procedure
      4. 6.2.4 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Specification Definitions
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Layout

8.1 Layout Guidelines

8.1.1 Power Planes

All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures that all power buses to the ADC are turned on and off simultaneously. This single source will be split into individual sections of the power plane, with individual decoupling and connection to the different power supply buses of the ADC. Due to the low voltage but relatively high supply current requirement, the optimal solution may be to use a switching regulator to provide an intermediate low voltage, which is then regulated down to the final ADC supply voltage by a linear regulator. Please refer to the documentation provided for the ADC12D1800RFRB for additional details on specific regulators that are recommended for this configuration.

Power for the ADC should be provided through a broad plane which is located on one layer adjacent to the ground plane(s). Placing the power and ground planes on adjacent layers will provide low impedance decoupling of the ADC supplies, especially at higher frequencies. The output of a linear regulator should feed into the power plane through a low impedance multi-via connection. The power plane should be split into individual power peninsulas near the ADC. Each peninsula should feed a particular power bus on the ADC, with decoupling for that power bus connecting the peninsula to the ground plane near each power / ground pin pair. Using this technique can be difficult on many printed circuit CAD tools. To work around this, zero ohm resistors can be used to connect the power source net to the individual nets for the different ADC power buses. As a final step, the zero ohm resistors can be removed and the plane and peninsulas can be connected manually after all other error checking is completed.

8.1.2 Bypass Capacitors

The general recommendation is to have one 100nF capacitor for each power / ground pin pair. The capacitors should be surface mount multi-layer ceramic chip capacitors similar to Panasonic part number ECJ-0EB1A104K.

8.1.3 Ground Planes

Grounding should be done using continuous full ground planes to minimize the impedance for all ground return paths, and provide the shortest possible image/return path for all signal traces.

8.1.4 Power System Example

The ADC12D1800RFRB uses continuous ground planes (except where clear areas are needed to provide appropriate impedance management for specific signals), see Figure 8-1. Power is provided on one plane, with the 1.9V ADC supply being split into multiple zones or peninsulas for the specific power buses of the ADC. Decoupling capacitors are connected between these power bus peninsulas and the adjacent ground planes using vias. The capacitors are located as close to the individual power / ground pin pairs of the ADC as possible. In most cases, this means the capacitors are located on the opposite side of the PCB to the ADC.

ADC12D1800RF 30164302.gifFigure 8-1 Power and Grounding Example

8.2 Layout Example

The following examples show layout-example plots. Figure 8-4 show a typical stack up for a 10 layer board.

ADC12D1800RF layout_example_1_top_snas518.gifFigure 8-2 ADC12D1800RF Layout Example 1 - Top Side and Inner Layers
ADC12D1800RF layout_example_1_bottom_snas518.gifFigure 8-3 ADC12D1800RF Layout Example 1 - Bottom Side and Inner Layers
ADC12D1800RF typ_stackup_snas518.gifFigure 8-4 ADC12D1800RF Typical Stackup - 10 Layer Board

8.3 Thermal Management

The Heat Slug Ball Grid Array (HSBGA) package is a modified version of the industry standard plastic BGA (Ball Grid Array) package. Inside the package, a copper heat spreader cap is attached to the substrate top with exposed metal in the center top area of the package. This results in a 20% improvement (typical) in thermal performance over the standard plastic BGA package.

ADC12D1800RF 30164309.gifFigure 8-5 HSBGA Conceptual Drawing

The center balls are connected to the bottom of the die by vias in the package substrate, Figure 8-5. This gives a low thermal resistance between the die and these balls. Connecting these balls to the PCB ground planes with a low thermal resistance path is the best way dissipate the heat from the ADC. These pins should also be connected to the ground plane via a low impedance path for electrical purposes. The direct connection to the ground planes is an easy method to spread heat away from the ADC. Along with the ground plane, the parallel power planes will provide additional thermal dissipation.

The center ground balls should be soldered down to the recommended ball pads (See SNOA021). These balls will have wide traces which in turn have vias which connect to the internal ground planes, and a bottom ground pad / pour if possible. This ensures a good ground is provided for these balls, and that the optimal heat transfer will occur between these balls and the PCB ground planes.

In spite of these package enhancements, analysis using the standard JEDEC JESD51-7 four-layer PCB thermal model shows that ambient temperatures must be limited to a max of 65°C to ensure a safe operating junction temperature for the ADC12D1800RF. However, most applications using the ADC12D1800RF will have a printed circuit board which is more complex than that used in JESD51-7. Typical circuit boards will have more layers than the JESD51-7 (eight or more), several of which will be used for ground and power planes. In those applications, the thermal resistance parameters of the ADC12D1800RF and the circuit board can be used to determine the actual safe ambient operating temperature up to a maximum of 85°C.

Three key parameters are provided to allow for modeling and calculations. Because there are two main thermal paths between the ADC die and external environment, the thermal resistance for each of these paths is provided. θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA package. θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of the HSBGA package. The final parameter is the allowed maximum junction temperature, which is TJ.

In other applications, a heat sink or other thermally conductive path can be added to the top of the HSBGA package to remove heat. In those cases, θJC1 can be used along with the thermal parameters for the heat sink or other thermal coupling added. Representative heat sinks which might be used with the ADC12D1800RF include the Cool Innovations p/n 3-1212XXG and similar products from other vendors. In many applications, the printed circuit board will provide the primary thermal path conducting heat away from the ADC package. In those cases, θJC2 can be used in conjunction with printed circuit board thermal modeling software to determine the allowed operating conditions that will maintain the die temperature below the maximum allowable limit. Additional dissipation can be achieved by coupling a heat sink to the copper pour area on the bottom side of the printed circuit board.

Typically, dissipation will occur through one predominant thermal path. In these cases, the following calculations can be used to determine the maximum safe ambient operating temperature:

TJ = TA + PD × (θJC+θCA)

TJ = TA + PC(MAX) × (θJC+θCA)

For θJC, the value for the primary thermal path in the given application environment should be used (θJC1 or θJC2). θCA is the thermal resistance from the case to ambient, which would typically be that of the heat sink used. Using this relationship and the desired ambient temperature, the required heat sink thermal resistance can be found. Alternately, the heat sink thermal resistance can be used to find the maximum ambient temperature. For more complex systems, thermal modeling software can be used to evaluate the printed circuit board system and determine the expected junction temperature given the total system dissipation and ambient temperature.