JAJSIL5B February   2020  – October 2024 ADC12DJ1600-Q1 , ADC12QJ1600-Q1 , ADC12SJ1600-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  ADC12xJ1600-Q1: Electrical Characteristics: Power Consumption
    7. 5.7  ADC12xJ1600-Q1: Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
6.4.4.5.1 Short Transport Test Pattern

Short transport test patterns send a predefined octet format that repeats every frame. The short transport test patterns for each JMODE are defined in this section.

Table 6-38 Short Transport Test Pattern for JMODE 0
OCTET01234567
NIBBLE0123456789101112131415
D00xF010xF020xF030xF040xF05T
D10xE110xE120xE130xE140xE15T
D2 (Dual or Quad only)0xD210xD220xD230xD240xD25T
D3 (Dual or Quad only)0xC310xC320xC330xC340xC35T
D4 (Quad only)0xB410xB420xB430xB440xB45T
D5 (Quad only)0xA510xA520xA530xA540xA55T
D6 (Quad only)0x9610x9620x9630x9640x965T
D7 (Quad only)0x8710x8720x8730x8740x875T
Table 6-39 Short Transport Test Pattern for JMODE 1
OCTET 0 1
NIBBLE 0 1 2 3
D0 0xF01 0xF
D1 0x02 0xE1
D2 (Dual or Quad only) 0x1 0xE12
D3 (Quad only) 0xD21 0xD
D4 (Quad only) 0x22 0xC3
D5 (Quad only) 0x1 0xC32
Table 6-40 Short Transport Test Pattern for JMODE 2
OCTET0
NIBBLE01
D00x01
D1 (Dual or Quad only)0x11
D2 (Quad only)0x21
D3 (Quad only)0x31
Table 6-41 Short Transport Test Pattern for JMODE 3
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 0x301 0x302 0x303 0x304
D1 (Dual or Quad only) 0x211 0x212 0x213 0x214
D2 (Quad only) 0x121 0x122 0x123 0x124
D3 (Quad only) 0x031 0x032 0x033 0x034
Table 6-42 Short Transport Test Pattern for JMODE 4
OCTET 0 1
NIBBLE 0 1 2 3
D0 0xF01 0xE
D1 (Dual or Quad only) 0x11 0xD2
D2 (Quad only) 0x1 0xC31
Table 6-43 Short Transport Test Pattern for JMODE 5
OCTET01
NIBBLE0123
D00x010x11
D1 (Quad only)0x210x31
Table 6-44 Short Transport Test Pattern for JMODE 6
OCTET 0 1
NIBBLE 0 1 2 3
D0 0xF01 0xF
D1 0x02 0xE1
D2 (Dual or Quad only) 0x1 0xE12
D3 (Quad only) 0xD21 0xD
D4 (Quad only) 0x22 0xC3
D5 (Quad only) 0x1 0xC32
Table 6-45 Short Transport Test Pattern for JMODE 7
OCTET0
NIBBLE01
D00x01
D1 (Dual or Quad only)0x11
D2 (Quad only)0x21
D3 (Quad only)0x31
Table 6-46 Short Transport Test Pattern for JMODE 8
OCTET012
NIBBLE012345
D00xF010xF02
D1 (Dual or Quad only)0xE110xE12
D2 (Quad only)0xD210xD22
D3 (Quad only)0xC310xC32
Table 6-47 Short Transport Test Pattern for JMODE 9
OCTET0
NIBBLE01
D00x01
D10x02
D2 (Dual or Quad only)0x11
D3 (Dual or Quad only)0x12
D4 (Quad only)0x21
D5 (Quad only)0x22
D6 (Quad only)0x31
D7 (Quad only)0x32
Table 6-48 Short Transport Test Pattern for JMODE 10
OCTET01234
NIBBLE0123456789
D00x3010x3020x3030x304
D10x2110x2120x2130x214
D2 (Dual or Quad only)0x1210x1220x1230x124
D3 (Dual or Quad only)0x0310x0320x0330x034
D4 (Quad only)0x3410x3420x3430x344
D5 (Quad only)0x2510x2520x2530x254
D6 (Quad only)0x1610x1620x1630x164
D7 (Quad only)0x0710x0720x0730x074
Table 6-49 Short Transport Test Pattern for JMODE 11
OCTET 0 1 2 3 4 5 6 7
NIBBLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 0xF01 0xF02 0xF03 0xF04 0xF05 T
D1 0xE11 0xE12 0xE13 0xE14 0xE15 T
D2 0xD21 0xD22 0xD23 0xD24 0xD25 T
D3 0xC31 0xC32 0xC33 0xC34 0xC35 T
D4 (Dual only) 0xB41 0xB42 0xB43 0xB44 0xB45 T
D5 (Dual only) 0xA51 0xA52 0xA53 0xA54 0xA55 T
D6 (Dual only) 0x961 0x962 0x963 0x964 0x965 T
D7 (Dual only) 0x871 0x872 0x873 0x874 0x875 T
Table 6-50 Short Transport Test Pattern for JMODE 12
OCTET0
NIBBLE01
D00x01
D10x02
D20x03
D30x04
D4 (Dual only)0x11
D5 (Dual only)0x12
D6 (Dual only)0x13
D7 (Dual only)0x14
Table 6-51 Short Transport Test Pattern for JMODE 13
OCTET 0 1 2 3 4
NIBBLE 0 1 2 3 4 5 6 7 8 9
D0 0x301 0x302 0x303 0x304
D1 0x211 0x212 0x213 0x214
D2 0x121 0x122 0x123 0x124
D3 0x031 0x032 0x033 0x034
D4 (Dual only) 0x341 0x342 0x343 0x344
D5 (Dual only) 0x251 0x252 0x253 0x254
D6 (Dual only) 0x161 0x162 0x163 0x164
D7 (Dual only) 0x071 0x072 0x073 0x074
Table 6-52 Short Transport Test Pattern for JMODE 14
OCTET012
NIBBLE012345
D00xF010xF02
D10xE110xE12
D2 (Dual or Quad only)0xD210xD22
D3 (Dual or Quad only)0xC310xC32
D4 (Quad only)0xB410xB42
D5 (Quad only)0xA510xA52
D6 (Quad only)0x9610x962
D7 (Quad only)0x8710x872
Table 6-53 Short Transport Test Pattern for JMODE 15
OCTET012
NIBBLE012345
D00xF010xF02
D10xE110xE12
D20xD210xD22
D30xC310xC32
D4 (Dual only)0xB410xB42
D5 (Dual only)0xA510xA52
D6 (Dual only)0x9610x962
D7 (Dual only)0x8710x872