JAJSIL5B February 2020 – October 2024 ADC12DJ1600-Q1 , ADC12QJ1600-Q1 , ADC12SJ1600-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| ADC SAMPLING CLOCK | ||||||
| fS | ADC core sampling clock frequency | High Performance Mode | 500(1) | 1600(1) | MHz | |
| Low Power Mode | 1000(1) | |||||
| ADC core minimum sampling clock frequency | Low Power Mode | 500(1) | ||||
| tS | ADC core sampling clock period | High Performance Mode | 625(1) | 2000(1) | ps | |
| Low Power Mode | 1000(1) | ps | ||||
| ADC core maximum sampling clock period | Low Power Mode | 2000(1) | ps | |||
| CLOCK INPUTS (CLK+, CLK–, SE_CLK) | ||||||
| fCLK | CLK± input frequency | PLL Disabled | 500 | 1600 | MHz | |
| PLL Enabled, PLLREF_SE = 0 | 50 | 500 | ||||
| fSE_CLK | SE_CLK input frequency | PLL Enabled, PLLREF_SE = 1 | 50 | 500 | MHz | |
| DC(CLKMIN) | Minimum Input clock duty cycle (CLK± and SE_CLK) | Input clock duty cycle (CLK± and SE_CLK) | 40% | |||
| DC(CLKMAX) | Maximum Input clock duty cycle (CLK± and SE_CLK) | 60% | ||||
| PHASE-LOCKED LOOP (PLL) AND VOLTAGE-CONTROLLED OSCILLATOR (VCO) | ||||||
| fPLLPFD | PLL phase-frequency detector (PFD) frequency | PLL Enabled | 50 | 500 | MHz | |
| fVCO | Closed-loop voltage-controlled oscillator (VCO) frequency | PLL Enabled | 7200 | 8200 | MHz | |
| SYSREF (SYSREF+, SYSREF–) | ||||||
| tINV(SYSREF) | Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(2) | 250 | ps | |||
| tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register | 0.05 | ps/°C | |||
| tINV(VA11) | Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register | -0.17 | ps/mV | |||
| tSTEP(SP) | Delay of SYSREF_POS LSB | SYSREF_ZOOM = 0 | 125 | ps | ||
| SYSREF_ZOOM = 1 | 69 | |||||
| DC(SYSREF) | SYSREF duty cycle (asserted) when using a periodic SYSREF signal | 50% | 55% | |||
| t(PH_SYS) | Minimum SYSREF± assertion duration after SYSREF± rising edge event | 4 | ns | |||
| JESD204C SYNC TIMING (SYNCSE) | ||||||
| SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS) | ||||||
| fCLK(SCLK) | Serial clock frequency | 0 | 15.625 | MHz | ||
| t(PH) | Serial clock high value pulse duration | 32 | ns | |||
| t(PL) | Serial clock low value pulse duration | 32 | ns | |||
| tSU(SCS) | Setup time from SCS to rising edge of SCLK | 25 | ns | |||
| tH(SCS) | Hold time from rising edge of SCLK to SCS | 3 | ns | |||
| tSU(SDI) | Setup time from SDI to rising edge of SCLK | 25 | ns | |||
| tH(SDI) | Hold time from rising edge of SCLK to SDI | 3 | ns | |||