JAJSEG6A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
B5_TIME_0 | |||||||
R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | B5_TIME_0 | R/W | Undefined | Time adjustment for bank 5 (applied when the ADC is configured for 0° clock phase). After reset, the factory-trimmed value can be read and adjusted as required. |