JAJSEG6A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
The ADC12DJ2700 uses the JESD204B high-speed serial interface for data converters to transfer data from the ADC to the receiving logic device. The ADC12DJ2700 serialized lanes are capable of operating up to 12.8 Gbps, slightly above the JESD204B maximum lane rate. A maximum of 16 lanes can be used to allow lower lane rates for interfacing with speed-limited logic devices. Figure 81 shows a simplified block diagram of the JESD204B interface protocol.
The various signals used in the JESD204B interface and the associated ADC12DJ2700 pin names are summarized briefly in Table 16 for reference.
SIGNAL NAME | ADC12DJ2700 PIN NAMES | DESCRIPTION |
---|---|---|
Data | DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–) | High-speed serialized data after 8b, 10b encoding |
SYNC | SYNCSE, TMSTP+, TMSTP– | Link initialization signal, toggles low to start code group synchronization (CGS) process |
Device clock | CLK+, CLK– | ADC sampling clock, also used for clocking digital logic and output serializers |
SYSREF | SYSREF+, SYSREF– | System timing reference used to deterministically reset the internal local multiframe counters in each JESD204B device |