JAJSDF5A June 2017 – April 2020 ADC12DJ3200
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
DEVICE (SAMPLING) CLOCK (CLK+, CLK–) | ||||||
fCLK | Input clock frequency (CLK+, CLK–), both single channel and dual channel modes(1) | 800 | 3200 | MHz | ||
SYSREF (SYSREF+, SYSREF–) | ||||||
tINV(SYSREF) | Width of invalid SYSREF capture region of CLK+/– period, indicating setup or hold time violation, as measured by SYSREF_POS status register(2) | 48 | ps | |||
tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register | 0 | ps/°C | |||
tINV(VA11) | Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register | 0.36 | ps/mV | |||
tSTEP(SP) | Delay of SYSREF_POS LSB | SYSREF_ZOOM = 0 | 77 | ps | ||
SYSREF_ZOOM = 1 | 24 | ps | ||||
t(PH_SYS) | Minimum SYSREF+/– assertion duration after SYSREF+/– rising edge event | 4 | ns | |||
t(PL_SYS) | Minimum SYSREF+/– deassertion duration after SYSREF+/– falling edge event | 1 | ns | |||
JESD204B SYNC TIMING (SYNCSE OR TMSTP+/–) | ||||||
tH(SYNCSE) | Minimum hold time from multi-frame boundary (SYSREF rising edge captured high) to de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1) | JMODE = 0, 2, 4, 6, 10, 13 or 15 | 21 | tCLK cycles | ||
JMODE = 1, 3, 5, 7, 9, 11, 14 or 16 | 17 | |||||
JMODE = 12, 17 or 18 | 9 | |||||
tSU(SYNCSE) | Minimum setup time from de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if SYNC_SEL = 1) to multi-frame boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1) | JMODE = 0, 2, 4, 6, 10, 13 or 15 | –2 | tCLK cycles | ||
JMODE = 1, 3, 5, 7, 9, 11, 14 or 16 | 2 | |||||
JMODE = 12, 17 or 18 | 10 | |||||
t(SYNCSE) | SYNCSE minimum assertion time to trigger link resynchronization | 4 | Frames | |||
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS) | ||||||
fCLK(SCLK) | Maximum serial clock frequency | 15.625 | MHz | |||
t(PH) | Minimum serial clock high value pulse width | 32 | ns | |||
t(PL) | Minimum serial clock low value pulse width | 32 | ns | |||
tSU(SCS) | Minimum setup time from SCS to rising edge of SCLK | 30 | ns | |||
tH(SCS) | Minimum hold time from rising edge of SCLK to SCS | 3 | ns | |||
tSU(SDI) | Minimum setup time from SDI to rising edge of SCLK | 30 | ns | |||
tH(SDI) | Minimum hold time from rising edge of SCLK to SDI | 3 | ns |