JAJSDF5A June 2017 – April 2020 ADC12DJ3200
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
B5_TIME_90 | |||||||
R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | B5_TIME_90 | R/W | Undefined | Time adjustment for bank 5 (applied when the ADC is configured for –90° clock phase). After reset, the factory-trimmed value can be read and adjusted as required. |