JAJSDF5A June 2017 – April 2020 ADC12DJ3200
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JSYNC_N | ||||||
R/W-0000 000 | R/W-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RESERVED | R/W | 0000 000 | RESERVED |
0 | JSYNC_N | R/W | 1 | Set this bit to 0 to request JESD204B synchronization (equivalent to the SYNCSE pin being asserted). For normal operation, leave this bit set to 1.
The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, the synchronization request cannot be de-asserted unless SYNC_SEL = 2 is programmed. |