JAJSDF5A June 2017 – April 2020 ADC12DJ3200
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JTEST | ||||||
R/W-0000 | R/W-0000 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0000 | RESERVED |
3-0 | JTEST | R/W | 0000 | 0: Test mode disabled; normal operation (default)
1: PRBS7 test mode 2: PRBS15 test mode 3: PRBS23 test mode 4: Ramp test mode 5: Transport layer test mode 6: D21.5 test mode 7: K28.5 test mode 8: Repeated ILA test mode 9: Modified RPAT test mode 10: Serial outputs held low 11: Serial outputs held high 12–15: Reserved Only change this register when JESD_EN is 0. |