JAJSDF5A June 2017 – April 2020 ADC12DJ3200
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTRA_LANE_A | EXTRA_SER_A | ||||||
R/W-0000 000 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | EXTRA_LANE_A | R/W | 0000 000 | Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_A(n) enables An (n = 1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_A = 1. |
0 | EXTRA_SER_A | R/W | 0 | 0: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to transmit data from the extra lanes. Important notes: Only change this register when JESD_EN = 0. The bit-rate and mode of the extra lanes are set by the JMODE and JTEST parameters. This register does not override the PD_CH register, so ensure that the link is enabled to use this feature. To enable serializer n, the lower number lanes 0 to n-1 must also be enabled, otherwise serializer n does not receive a clock. |