The high speed digital path of ADC12DJ3200QML-SP, including the DDC block and JESD204B block, is susceptible to radiation events. The following recommendations are provided to allow automatic recovery and to improve the recovery time of the JESD204B interface block of ADC12DJ3200QML-SP after being upset.

• Always use a continuous, periodic SYSREF in order to quickly recover internal clocks and counters. Set the period to be long enough to limit spurious performance degradation caused by coupling, but short enough to recover within the system requirements. SYSREF will help both the transmitter (ADC12DJ3200QML-SP) and receiver (FPGA or ASIC) recover after an SEU. SYSREF sets an upper bound for the time the link takes to discover a frame or multi-frame misalignment. As a minimum requirement, SYSREF must be activated when the receiver asserts the JESD204B SYNC signal.
• The receiver (FPGA or ASIC) must perform frame and multiframe alignment monitoring. Monitoring should include looking for misplaced or missing end-of-frame and end-of-multiframe characters. Misplaced characters are those that occur in the incorrect spot of a frame or multiframe, meaning not the last character of a frame or multiframe. Missing characters are those that the receiver deems should be included at the end of a frame or multiframe based on the character replacement rules of JESD204B. When two or more misplaced or missing characters are found (without receiving any in the correct position), the link should be reestablished by asserting SYNC to restart the CGS and ILAS processes.
• Enable scrambling to make sure the alignment characters are generated with consistent probabilities independent of the ADC data. Not using scrambling could result in long recovery times after a shift in frame or multiframe alignment.
• Make sure that the receiver frame-alignment state machine is implemented according to the JESD204B standard, including support for reinitialization over the data interface.  If the transmitter (ADC12DJ3200QML-SP) re-initializes the link (indicated by sending K28.5 characters without the receiver asserting the SYNC signal) the receiver should transition to the initial frame and lane alignment states.
• Additional robustness can be achieved in the 12-bit, DDC bypass JMODEs by monitoring the four tail bits at the end of each frame. Missing or misplaced tail bits can be treated the same as a frame misalignment error.

The accumulators of the numerically-controlled oscillators (NCOs) used by the DDC block are also susceptible to upsets. An upset of the NCO phase can be detected by using the NCO upset alarm feature described in Section 7.3.7.1. After an upset has been detected, the NCO must be reinitialized if phase synchronization between multiple ADC12DJ3200QML-SP devices is required. A more robust solution can be achieved if the NCO frequency is chosen to be a harmonic of the SYSREF frequency (integer related to the SYSREF frequency) and NCO synchronization using SYSREF (AC coupled) described in NCO Phase Synchronization is used. This allows SYSREF to automatically reset the NCO phase after an upset and automatically recovers the phase synchronization between multiple ADC12DJ3200QML-SP devices without having to resynchronize all ADC12DJ3200QML-SP devices in the system. This condition is met if f_NCO = n × f_SYSREF.