JAJSOE7D June 2022 – June 2024 ADC12DJ5200-EP
PRODUCTION DATA
ADC12DJ5200-EP can operate with subclass 0 compatibility provided that multi-ADC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as normal to initiate the CGS and ILAS in 8B/10B mode.