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ADC12DJ5200-EP デバイスは、RF サンプリング、ギガ サンプルの A/D コンバータ (ADC) で、DC から 10GHz 超までの入力周波数を直接サンプリングできます。ADC12DJ5200-EP はデュアル チャネル 5.2GSPS の ADC、またはシングル チャネル 10.4GSPS の ADC として構成できます。使用可能な入力周波数帯域が最高 10GHz であるため、L バンド、S バンド、C バンド、X バンドを直接 RF サンプリングでき、多様な周波数に対応したシステムを実現できます。
ADC12DJ5200-EP は、最大 17.16Gbps のライン速度をサポートする最大 16 個のシリアル化されたレーンを備えた、高速な JESD204C 出力インターフェイスを使っています。JESD204C subclass-1 により、決定論的レイテンシおよびマルチデバイス同期をサポートしています。JESD204C インターフェイスは、ライン速度とレーン数との間でトレードオフのバランスを取るように構成できます。8b/10b と 64b/66b の両方のデータ エンコードをサポートしています。64B/66B エンコードでは、前方エラー訂正 (FEC) によるビット エラー率の改善をサポートしています。このインターフェイスは、JESD204B レシーバと下位互換性があります。
ノイズなしのアパーチャ遅延調整や、SYSREF ウィンドウ処理などの革新的な同期機能により、マルチ チャネル アプリケーションのシステム設計を簡素化できます。オプションのデジタル ダウン コンバータ (DDC) を使用すると、ベースバンドへのデジタル変換を実行でき、またインターフェイス速度を低減できます。プログラム可能な FIR フィルタにより、オンチップのイコライゼーションが可能です。
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | A1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7 | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
BG | C3 | O | Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
CALSTAT | F7 | O | Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used. |
CALTRIG | E7 | I | Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used. |
CLK+ | F1 | I | Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. |
CLK– | G1 | I | Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best performance. |
DA0+ | E12 | O | High-speed serialized data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA0– | F12 | O | High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA1+ | C12 | O | High-speed serialized data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA1– | D12 | O | High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA2+ | A10 | O | High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA2– | A11 | O | High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA3+ | A8 | O | High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA3– | A9 | O | High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA4+ | E11 | O | High-speed serialized data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA4– | F11 | O | High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA5+ | C11 | O | High-speed serialized data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA5– | D11 | O | High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA6+ | B10 | O | High-speed serialized data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. This pin can be left disconnected if not used. |
DA6– | B11 | O | High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA7+ | B8 | O | High-speed serialized data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DA7– | B9 | O | High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB0+ | H12 | O | High-speed serialized data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB0– | G12 | O | High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB1+ | K12 | O | High-speed serialized data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB1– | J12 | O | High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB2+ | M10 | O | High-speed serialized data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB2– | M11 | O | High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB3+ | M8 | O | High-speed serialized data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB3– | M9 | O | High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used. |
DB4+ | H11 | O | High-speed serialized data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB4– | G11 | O | High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB5+ | K11 | O | High-speed serialized data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB5– | J11 | O | High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB6+ | L10 | O | High-speed serialized data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB6– | L11 | O | High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB7+ | L8 | O | High-speed serialized data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DB7– | L9 | O | High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used, or connected to any voltage level between GND (0V) and VD11 (1.1V) using 0 OHM to 1MOHM resistors. |
DGND | A12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12 | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
INA+ | A4 | I | Channel A analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
INA– | A5 | I | Channel A analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. |
INB+ | M4 | I | Channel B analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
INB– | M5 | I | Channel B analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INB+ for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. |
NCOA0 | C7 | I |
LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used. |
NCOA1 | D7 | I | MSB of NCO selection control for DDC A. Tie this pin to GND if not used. |
NCOB0 | K7 | I |
LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used. |
NCOB1 | J7 | I |
MSB of NCO selection control for DDC B. Tie this pin to GND if not used. |
ORA0 | C8 | O | Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORA1 | D8 | O | Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORB0 | K8 | O | Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORB1 | J8 | O | Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
PD | K6 | I | This pin disables all analog circuits and serializer outputs when set high for temperature diode calibration or to reduce power consumption when the device is not being used. Tie this pin to GND if not used. |
SCLK | F8 | I | Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. |
SCS | E8 | I | Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ pullup resistor to VD11. |
SDI | G8 | I | Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. |
SDO | H8 | O | Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used. |
SYNCSE | C2 | I | Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do not use the SYNC signal for initialization, however it may be used for NCO synchronization. When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used as the JESD204C SYNC signal. |
SYSREF+ | K1 | I | The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table. |
SYSREF– | L1 | I | SYSREF negative input |
TDIODE+ | K2 | I | Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used. |
TDIODE– | K3 | I | Temperature diode negative (cathode) connection. This pin can be left disconnected if not used. |
TMSTP+ | B1 | I | Timestamp
input positive connection or differential JESD204C
SYNC positive connection. This input is a
timestamp input, used to mark a specific sample, when TIMESTAMP_EN
is set to 1. This differential input is used as the JESD204C SYNC
signal input when SYNC_SEL is set 1. This input can be used as both
a timestamp and differential SYNC input at the same time, allowing
feedback of the SYNC signal using the timestamp mechanism. TMSTP±
uses active low signaling when used as a JESD204C SYNC. For
additional usage information, see the Timestamp section. TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC and DC coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required. |
TMSTP– | C1 | I | Timestamp input positive connection or differential JESD204C SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required. |
VA11 | C5, D2, D3, D5, E5, F5, G5, H5, J2, J3, J5, K5 | I | 1.1-V analog supply |
VA19 | C4, D4, E2, E3, E4, F4, G4, H2, H3, H4, J4, K4 | I | 1.9-V analog supply |
VD11 | C9, C10, E9, E10, G7, H7, H9, H10, K9, K10 | I | 1.1-V digital supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD | Supply voltage range | VA19(2) | –0.3 | 2.35 | V |
VA11(2) | –0.3 | 1.32 | |||
VD11(3) | –0.3 | 1.32 | |||
Voltage between VD11 and VA11 | –1.32 | 1.32 | |||
VGND | Voltage between AGND and DGND | –0.1 | 0.1 | V | |
VPIN | Pin voltage range | DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–, TMSTP+, TMSTP–(3) | –0.5 | VD11 + 0.5(5) | V |
CLK+, CLK–, SYSREF+, SYSREF–(2) | –0.5 | VA11 + 0.5(4) | |||
BG, TDIODE+, TDIODE–(2) | –0.5 | VA19 + 0.5(6) | |||
INA+, INA–, INB+, INB–(2) | –1 | 1 | |||
CALSTAT, CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE(2) | –0.5 | VA19 + 0.5(6) | |||
IMAX(ANY) | Peak input current (any input except INA+, INA–, INB+, INB–) | –25 | 25 | mA | |
IMAX(INx) | Peak input current (INA+, INA–, INB+, INB–) | –50 | 50 | mA | |
PMAX(INx) | Peak RF input power (INA+, INA–, INB+, INB–) | differential with ZS-DIFF = 100 Ω, up to 21 days(7) | 26.5 | dBm | |
Single-ended with ZS-SE = 50 Ω | 16.4 | dBm | |||
IMAX(ALL) | Peak total input current (sum of absolute value of all currents forced in or out, not including power-supply current) | 100 | mA | ||
Tj | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |