8.2.1 RF Sampling Receiver

An RF Sampling Receiver is used to directly sample a signal in the RF frequency range and provide the data for the captured signal to downstream processing. The wide input bandwidth, high sampling rate, and DDC features of the ADC12J1600 and ADC12J2700 make them ideally suited for this application.

Figure 109. Simplified Schematic

8.2.1.3 Application Curves

The following curves show an RF signal at 2497.97 MHz captured at a sample rate of 1600 MSPS. Figure 110 shows the spectrum for the full Nyquist band. Figure 111 shows the spectrum for the output data in decimate-by-32 mode with ƒ_(NCO) equal to 700 MHz. Figure 111 shows the ability to provide only the spectrum of interest in the decimated output data. Figure 111 also shows how proper selection of the sampling rate can ensure interleaving tones are outside the band of interest and outside the decimated frequency range. Lastly, Figure 111 shows the reduction in the noise floor provided by the processing gain of decimation.

DDC Bypass Mode		ƒS = 1600 MSPS
FIN = 2497.97 MHz at –1 dBFS

Figure 110. Spectrum — DDC Bypass Mode

ƒS = 1600 MSPS		ƒ(NCO) = 2500 MHz
FIN = 2497.97 MHz at –1 dBFS

Figure 111. Spectrum — Decimate-by-32

8.2.2 Oscilloscope

The ADC12J1600 and ADC12J2700 devices are equally well-suited for high-speed time-domain applications such as oscilloscopes. The following typical application is for a generic high-speed oscilloscope. Adjustable gain is provided by the front-end resistor ladder and selection mux, and the gain adjustments of the LMH6518 device. Additional gain fine-tuning can be achieved using the full-scale range adjustment features of the ADC.

Figure 112. Simplified Schematic for an Oscilloscope

8.2.2.3 Application Curves

The following curves show the time-domain sample data for a 150-MHz input signal at –1 dBFS, sampled at 1600 MSPS using the ADC12J1600 device. Figure 113 shows the raw time-domain data. Figure 114 shows the spectrum of the captured signal which shows the additional capability of a 12-bit ADC oscilloscope to provide basic spectrum-analysis functions with reasonable performance.

FIN = 147.97 MHz at –1 dBFS

ƒS = 1600 MSPS

Figure 113. Raw Time-Domain Data

FIN = 147.97 MHz at –1 dBFS

ƒS = 1600 MSPS

Figure 114. Captured Signal Spectrum

8.3.1 JESD204B Startup Sequence

The JESD204B interface requires a specific startup and alignment sequence. The general order of that sequence is listed in the following steps.

1. Power up or reset the ADC12J1600 and ADC12J2700 devices.
2. Program JESD_EN = 0 to shut down the link and enable configuration changes.
3. Program DECIMATE, SCRAM_EN, KM1 and DDR to the desired settings.
4. Configure the device calibration settings as desired, and initiate a calibration (set CAL_SFT = 1).
5. Program JESD_EN = 1 to enable the link.
6. Apply at least one SYSREF rising edge to establish the LMFC phase.
7. Assert SYNC~ from the data receiver to initiate link communications.
8. After the JESD204B receiver has established code group synchronization, SYNC~ is de-asserted and the ILA process begins.
9. Immediately following the end of the ILA sequence normal data output begins.

8.4.1 Common Application Pitfalls

Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, an input must not go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits even on a transient basis can cause faulty, or erratic, operation and can impair device reliability. High-speed digital circuits exhibiting undershoot that goes more than a volt below ground is common. To control overshoot, the impedance of high-speed lines must be controlled and these lines must be terminated in the characteristic impedance.

Care must be taken not to overdrive the inputs of the ADC12J1600 and ADC12J2700 devices. Such practice can lead to conversion inaccuracies and even to device damage.

Incorrect analog input common-mode voltage in the DC-coupled mode. As described in the The Analog Inputs and DC Coupled Input Usage sections, the input common-mode voltage (V_CMI) must remain the specified range as referenced to the VCMO pin, which has a variability with temperature that must also be tracked. Distortion performance is degraded if the input common mode voltage is outside the specified V_CMI range.

Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier to drive the ADC12J1600 and ADC12J2700 devices because many high-speed amplifiers have higher distortion than the ADC12J1600 and ADC12J2700 devices which results in overall system performance degradation.

Driving the clock input with an excessively high level signal. The ADC input clock level must not exceed the level described in the Recommended Operating Conditions table because the input offset can change if these levels are exceeded.

Inadequate input clock levels. As described in the Using the Serial Interface section, insufficient input clock levels can result in poor performance. Excessive input-clock levels can result in the introduction of an input offset.

Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other signals coupled to the input clock signal trace. These pitfalls cause the sampling interval to vary which causes excessive output noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in the Thermal Management section, providing adequate heat removal is important to ensure device reliability. Adequate heat removal is primarily provided by properly connecting the thermal pad to the circuit board ground planes. Multiple vias should be arranged in a grid pattern in the area of the thermal pad. These vias will connect the topside pad to the internal ground planes and to a copper pour area on the opposite side of the printed circuit board.