SLAS969 Data sheet

SLAS969D January 2014 – October 2017 ADC12J1600 , ADC12J2700

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7 Detailed Description

7.1 Overview

The ADC12J1600 and ADC12J2700 devices are an ultra-wideband sampling and digital tuning subsystem. The devices combine a very-wideband and high sampling-rate ADC front-end with a configurable digital-down conversion block. This combination provides the necessary features to facilitate the development of flexible software-defined radio products for a wide range of communications applications.

The ADC12J1600 and ADC12J2700 devices are based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture that results in very high sampling rate, very good dynamic performance, and relatively low-power consumption. This ADC core is followed by a configurable DDC block which is implemented on a small geometry CMOS. The DDC block provides a range of decimation settings that allow the product to work in ultra-wideband, wideband, and more-narrow-band receive systems. The output data from the DDC block is transmitted through a JESD204B-compatible multi-lane serial-output system. This system minimizes the number of data pairs required to convey the output data to the downstream processing circuitry.

7.2 Functional Block Diagram

Figure 63. DDC Details Block Diagram

7.3 Feature Description

7.3.1 Signal Acquisition

The analog input is sampled on the rising edge of CLK and the digital equivalent of that data is available in the serialized datastream t_(LAT) or t_{(LAT_DDC)} input clock cycles later.

The ADC12J1600 and ADC12J2700 devices convert as long as the input clock signal is present. The fully-differential comparator design and the innovative design of the sample-and-hold amplifier, together with calibration, enables very good performance at input frequencies beyond 3 GHz. The ADC12J1600 and ADC12J2700 data is output on a high-speed serial JESD204B interface.

7.3.2 The Analog Inputs

A differential input signal must be used to drive the ADC12J1600 and ADC12J2700 devices. Operation with a single-ended signal is not recommended as performance suffers. The input signals can be either be AC coupled or DC coupled. The analog inputs are internally connected to the V_CMO bias voltage. When DC-coupled input signals are used, the common mode voltage of the applied signal must meet the device Input common mode requirements. See V_CMI in the Recommended Operating Conditions table.

The full-scale input range for each converter can be adjusted through the serial interface. See the Full Scale Range Adjust section.

The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at sampling ADC inputs is not required. If an amplifier circuit before the ADC is desired, use care when selecting an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the application. If gain is not required, a balun (balanced-to-unbalanced transformer) is generally used to provide single ended (SE) to differential conversion.

The input impedance of VIN± consists of two 50-Ω resistors in series between the inputs and a capacitance from each of these inputs to ground. A resistance of approximately 20 kΩ exists from the center point of the 50-Ω resistors to the on-chip V_CMO providing self-biasing for AC-coupled applications.

Performance is good in both DC-coupled mode and AC coupled mode, provided the common-mode voltage at the analog input is within specifications.

7.3.2.1 Input Clamp

The ADC12J1600 and ADC12J2700 maximum DC input voltage is limited to the range 0 to 2 V to prevent damage to the device. To help maintain these limits, an active input clamping circuit is incorporated which sources or sinks input currents up to ±50 mA. The clamping circuit is enabled by default and is controlled via the Input_Clamp_EN bit (register 0x034, bit 5). The protection provided by this circuit is limited as follows:

Shunt current-clamping is only effective for non-zero source impedances.
At frequencies above 3 GHz the clamping is ineffective because of the finite turn-on and turn-off time of the switch.

With these limitations in mind, analysis has been done to determine the allowable input signal levels as a function of input frequency when the Input Clamp is enabled, assuming the source impedance matches the input impedance of the device (100-Ω differential). This information is incorporated in the Absolute Maximum Ratings table.

7.3.2.2 AC Coupled Input Usage

The easiest way to accomplish SE-to-differential conversion for AC-coupled signals is with an appropriate balun.

Figure 64. Single-Ended-to-Differential Signal Conversion With a Balun

Figure 64 shows a generic depiction of a SE-to-differential signal conversion using a balun. The circuitry specific to the balun depends on the type of balun selected and the overall board layout. TI recommends that the system designer contact the manufacturer of the selected balun to aid in designing the best performing single-ended to differential conversion circuit using that particular balun.

When selecting a balun, understanding the input architecture of the ADC is important. Specific balun parameters must be considered. The balun must match the impedance of the analog source to the on-chip 100-Ω differential input termination of the ADC12J1600 and ADC12J2700 devices. The range of this input termination resistor is described in the Electrical Characteristics table as the specification R_ID.

Also, as a result of the ADC architecture, the phase and amplitude balance are important. The lowest possible phase and amplitude imbalance is desired when selecting a balun. The phase imbalance must be no more than ±2.5° and the amplitude imbalance must be limited to less than 1 dB at the desired input frequency range.

Finally, when selecting a balun, the voltage standing-wave ratio (VSWR), bandwidth, and insertion loss of the balun must also be considered. The VSWR aids in determining the overall transmission line termination capability of the balun when interfacing to the ADC input. The insertion loss must be considered so that the signal at the balun output is within the specified input range of the ADC as described in the Electrical Characteristics table as the specification V_ID.

Table 1 lists the recommended baluns for specific signal frequency ranges.

Table 1. Balun Recommendations

MINIMUM FREQUENCY (MHz)	MAXIMUM FREQUENCY (MHz)	IMPEDANCE RATIO	PART NUMBER	MANUFACTURER
4.5	3000	1:1	TC1-1-13MA+	Mini-Circuits
400	3000	1:2	B0430J50100AHF	Anaren
30	1800	1:2	ADTL2-18+	Mini-Circuits
10	4000	1:2	TCM2-43X+	Mini-Circuits

7.3.2.3 DC Coupled Input Usage

When a DC-coupled signal source is used, the common mode voltage of the applied signal must be within a specified range (V_CMI). To achieve this range, the common mode of the driver should be based on the VCMO output provided for this purpose.

Full-scale distortion performance degrades as the input common-mode voltage deviates from VCMO. Therefore, maintaining the input common-mode voltage within the V_CMI range is important.

Table 2 lists the recommended amplifiers for DC-coupled usage or if AC-coupling with gain is required.

Table 2. Amplifier Recommendations

–3-dB BANDWIDTH (MHz)	MIN GAIN (dB)	MAX GAIN (dB)	GAIN TYPE	PART NUMBER
7000	16	16	Fixed	LMH3401
2800	0	17	Resistor set	LMH6554
2400	6	26	Digital programmable	LMH6881
900	–1.16	38.8	Digital programmable	LMH6518

7.3.2.4 Handling Single-Ended Input Signals

The ADC12J1600 and ADC12J2700 devices have no provision to adequately process single-ended input signals. The best way to handle single-ended signals is to convert these signals to balanced differential signals before presenting the signals to the ADC.

7.3.3 Clocking

The ADC12J1600 and ADC12J2700 devices have a differential clock input, DEVCLK+ and DEVCLK–, that must be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as shown in Figure 65.

Figure 65. Differential Sample-Clock Connection

The differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at the clock source of that 100-Ω characteristic impedance. The input clock line must be as short and direct as possible. The ADC12J1600 and ADC12J2700 clock input is internally terminated with an untrimmed 100-Ω resistance.

Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range specified in the Electrical Characteristics table.

The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J1600 and ADC12J2700 devices feature a duty-cycle clock-correction circuit which maintains performance over temperature. The ADC meets the performance specification when the input clock high times and low times are maintained as specified in the Electrical Characteristics table.

High-speed high-performance ADCs such as the ADC12J1600 and ADC12J2700 devices require a very-stable input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR.

Equation 1. ADC12J1600 ADC12J2700 eq_01_slas989.gif

where

RMS_tot(J) is the RMS total of all jitter sources in seconds
V_I(PP) is the peak-to-peak analog input signal
V_FSR is the full-scale range of the ADC
n is the ADC resolution in bits
F_IN is the maximum input frequency, in Hertz, at the ADC analog input

Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources, including that from the clock source, the jitter added by noise coupling at board level and that added internally by the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the externally-added input clock jitter and the jitter added by any circuitry to the analog signal.

Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code other than the expected 2048 when both input pins are at the same potential.

7.3.4 Over-Range Function

To ensure that system-gain management has the quickest-possible response time, a low-latency configurable over-range function is included. The over-range function works by monitoring the raw 12-bit samples exiting the ADC module. The upper 8 bits of the magnitude of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. The following table lists how a raw ADC value is converted to an absolute value for a comparison of the thresholds.

ADC SAMPLE (OFFSET BINARY)	ADC SAMPLE (2's COMPLEMENT)	ABSOLUTE VALUE	UPPER 8 BITS USED FOR COMPARISON
1111 1111 1111 (4095)	0111 1111 1111 (+2047)	111 1111 1111 (2047)	1111 1111 (255)
1111 1111 0000 (4080)	0111 1111 0000 (+2032)	111 1111 0000 (2032)	1111 1110 (254)
1000 0000 0000 (2048)	0000 0000 0000 (0)	000 0000 0000 (0)	0000 0000 (0)
0000 0001 0000 (16)	1000 0001 0000 (-2032)	111 1111 0000 (2032)	1111 1110 (254)
0000 0000 0000 (0)	1000 0000 0000 (-2048)	111 1111 1111 (2047)	1111 1111 (255)

If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 threshold during the monitoring period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. The resulting over-range bits are embedded into the complex output data samples and output on OR_T0 and OR_T1. Table 3 lists the outputs, related data samples, threshold settings and the monitoring period equation.

Table 3. Threshold and Monitor Period for Embedded OR Bits

EMBEDDED OVER-RANGE OUTPUTS	ASSOCIATED THRESHOLD	ASSOCIATED SAMPLES	MONITORING PERIOD (ADC SAMPLES)
OR_T0	OVR_T0	In-Phase (I) samples	2^OVR_N⁽¹⁾
OR_T1	OVR_T1	Quadrature (Q) samples	2^OVR_N⁽¹⁾

(1) OVR_N is the monitoring period register setting.

Table 4. Over-Range Monitoring Period

OVR_N	MONITORING PERIOD
0	1
1	2
2	4
3	8
4	16
5	32
6	64
7	128

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 (−12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS).

The OR_T0 threshold is embedded as the LSB along with the upper 15 bits of every complex I sample. The OR_T1 threshold is embedded as the LSB along with the upper 15 bits of every complex Q sample.

7.3.5 ADC Core Features

7.3.5.1 The Reference Voltage

The reference voltage for the ADC12J1600 and ADC12J2700 devices is derived from an internal bandgap reference. A buffered version of the reference voltage is available at the VBG pin for user convenience. This output has an output-current capability of ±100 μA. The VBG output must be buffered if more current is required. No provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register settings.

7.3.5.2 Common-Mode Voltage Generation

The internal reference voltage is used to generate a stable common-mode voltage reference for the analog Inputs and the DEVCLK and SYSREF differential-clock inputs.

7.3.5.3 Bias Current Generation

An external bias resistor, in combination with the on-chip voltage reference is used to provide an accurate and stable source of bias currents for internal circuitry. Using an external accurate resistor minimizes variation in device power consumption and performance.

7.3.5.4 Full Scale Range Adjust

The ADC input full-scale range can be adjusted through the GAIN_FS register setting (registers 0x022 and 0x023). The adjustment range is approximately 500 mV_PP to 950 mV_PP. The full-scale range adjustment is useful for matching the input-signal amplitude to the ADC full scale, or to match the full-scale range of multiple ADCs when developing a multi-converter system.

7.3.5.5 Offset Adjust

The ADC-input offset voltage can be adjusted through the OFFSET_FS register setting (registers 0x025 and 0x026). The adjustment range is approximately 28 mV to –28 mV differential.

NOTE

Offset adjust has no effect when background calibration mode is enabled.

7.3.5.6 Power-Down

The power-down bit (PD) allows the ADC12J1600 and ADC12J2700 devices to be entirely powered down. The serial data output drivers are disabled when PD is high. When the device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline and decimation filters contain meaningless information and must be flushed.

7.3.5.7 Built-In Temperature Monitor Diode

A built-in thermal monitoring diode junction is made available on the TDIODE+ and TDIODE– pins. This diode facilitates temperature monitoring and characterization of the device in higher ambient temperature environments. While the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline measurement at a known ambient or board temperature with the device in power-down (PD) mode. Recommended monitoring ICs include the LM95233 device and similar remote-diode temperature monitoring products from Texas Instruments.

7.3.6 Digital Down Converter (DDC)

The digitized data is the input to the digital down-converter block. This block provides frequency conversion and decimation filtering to allow a specific range of frequencies to be selected and output in the digital data stream.

7.3.6.1 NCO/Mixer

The DDC contains a complex numerically-controlled oscillator and a complex mixer. The oscillator generates a complex exponential sequence shown in Equation 2.

Equation 2. x[n] = e^jωn

The frequency (ω) is specified by the a 32-bit register setting. The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down to 0 Hz.

7.3.6.2 NCO Settings

7.3.6.2.1 NCO Frequency Phase Selection

Within the DDC, eight different frequency and phase settings are always available for use. Each of the eight settings uses a different phase accumulator within the NCO. Because all eight phase accumulators are continuously running independently, rapid switching between different NCO frequencies is possible allowing rapid tuning of different signals.

The specific frequency-phase pair in use is selected through either the NCO_x input pins, or the NCO_SEL configuration bits (register 0x20D, bits 2:0). The CFG_MODE bit (register 0x20C, bit 0) is used to choose whether the input pins or selection bits are used. When the CFG_MODE bit is set to 0, the NCO_x input pins select the active NCO frequency and phase setting. When the CFG_MODE bit is set to 1, the NCO_SEL register settings select the active NCO frequency and phase setting.

The frequency for each phase accumulator is programmed independently through the NCO_FREQn (and optionally NCO_RDIV) settings. The phase offset for each accumulator is programmed independently through the NCO_PHASEn register settings.

7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)

When the CFG_MODE bit is set to 0, the state of these three inputs determines the active NCO frequency and phase accumulator settings.

7.3.6.2.3 NCO_SEL Bits (2:0)

When the CFG_MODE bit is set to 1, the state of these register bits determines the active NCO frequency and phase accumulator settings.

7.3.6.2.4 NCO Frequency Setting (Eight Total)

7.3.6.2.4.1 Basic NCO Frequency-Setting Mode

In basic NCO frequency-setting mode, the NCO frequency setting is set by the 32-bit register value, NCO_FREQn (n = preset 0 trough 7, see the NCO Frequency (Preset x) Register section).

Equation 3. (n = 0 – 7) ƒ_(NCO) = NCO_FREQn × 2^–32 × ƒ_(DEVCLK)

NOTE

Changing the register setting after the JESD204B interface is running results in non-deterministic NCO phase. If deterministic phase is required, the JESD204B link must be re-initialized after changing the register setting. See the Multiple ADC Synchronization section.

7.3.6.2.4.2 Rational NCO Frequency Setting Mode

In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized, but sometimes an application requires very specific frequencies that fall between two frequency steps. For example with ƒ_S equal to 2457.6 MHz and a desired ƒ_(NCO) equal to 5.02 MHz the value for NCO_FREQ is 8773085.867. Truncating the fractional portion results in an ƒ_(NCO) equal to 5.0199995 MHz, which is not the desired frequency.

To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at specific frequencies without error. First, select a frequency step size (ƒ_(STEP)) that is appropriate for the NCO frequency steps required. The typical value of ƒ_(STEP) is 10 kHz. Next, program the NCO_RDIV value according to Equation 4.

Equation 4. ADC12J1600 ADC12J2700 eq_02_slas989.gif

The result of Equation 4 must be an integer value. If the value is not an integer, adjust either of the parameters until the result in an integer value.

For example, select a value of 1920 for NCO_RDIV.

NOTE

NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are not recommended.

Now use Equation 5 to calculate the NCO_FREQ register value.

Equation 5. ADC12J1600 ADC12J2700 eq_03_slas989.gif

Alternatively, the following equations can be used:

Equation 6. ADC12J1600 ADC12J2700 eq_04_slas989.gif

Equation 7. ADC12J1600 ADC12J2700 eq_05_slas989.gif

Table 5. Common NCO_RDIV Values (For 10-kHz Frequency Steps)

ƒ_(DEVCLK) (MHz)	NCO_RDIV
2457.6	1920
1966.08	1536
1474.56	1152
1228.8	960

7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)

The NCO phase-offset setting is set by the 16-bit register value NCO_PHASEn (n = preset 0 trough 7, see the NCO Phase (Preset x) Register section). The value is left-justified into a 32-bit field and then added to the phase accumulator.

Use Equation 8 to calculate the phase offset in radians.

Equation 8. NCO_PHASEn × 2^–16 × 2 × π

NOTE

7.3.6.2.6 Programmable DDC Delay

The DDC Filter elements incorporate a programmable sample delay. The delay can be programmed from 0 to (decimation setting – 0.5) ADC sample periods. The delay step-size is 0.5 ADC sample periods. The delay settings are programmed through the DDC_DLYn parameter.

Table 6. Programmable DDC Delay Range

D (Decimation Setting)	Min Delay (t_(DEVCLK))	Max Delay (t_(DEVCLK))
4	0	3.5
8	0	7.5
10	0	9.5
16	0	15.5
20	0	19.5
32	0	31.5

7.3.6.3 Decimation Filters

The decimation filters are arranged to provide a programmable overall decimation of 4, 8, 10, 16, 20, or 32. The input and output of each filter is complex. The output data consists of 15-bit complex baseband information. Table 7 lists the effective output sample rates.

Table 7. Output Sample Rates

DECIMATION SETTING	COMPLEX SAMPLE OUTPUT RATE AND RESULTING BANDWIDTH (OUTPUT SAMPLE = 15-BIT I + 15-BIT Q + 2-BIT OR)
	ƒ_(DEVCLK)			ƒ_(DEVCLK) = 4000 MHz
	OUTPUT RATE (MSPS)	RAW OUTPUT BANDWIDTH (MHz)	ALIAS PROTECTED BANDWIDTH (MHz)	OUTPUT RATE (MSPS)	RAW OUTPUT BANDWIDTH (MHz)	ALIAS PROTECTED BANDWIDTH (MHz)
4	ƒ_(DEVCLK) / 4	ƒ_(DEVCLK) / 4	0.8 × ƒ_(DEVCLK) / 4	1000	1000	800
8	ƒ_(DEVCLK) / 8	ƒ_(DEVCLK)N / 8	0.8 × ƒ_(DEVCLK) / 8	500	500	400
10	ƒ_(DEVCLK) / 10	ƒ_(DEVCLK) / 10	0.8 × ƒ_(DEVCLK) / 10	400	400	320
16	ƒ_(DEVCLK) / 16	ƒ_(DEVCLK) / 16	0.8 × ƒ_(DEVCLK) / 16	250	250	200
20	ƒ_(DEVCLK) / 20	ƒ_(DEVCLK) / 20	0.8 × ƒ_(DEVCLK) / 20	200	200	160
32	ƒ_(DEVCLK) / 32	ƒ_(DEVCLK) / 32	0.8 × ƒ_(DEVCLK) / 32	125	125	100

For maximum efficiency a group of high speed filter blocks are implemented with specific blocks used for each decimation setting. The first table below describes the combination of filter blocks used for each decimation setting. The next table lists the coefficient details and decimation factor of each filter block.

Table 8. Decimation Mode Filter Usage

Decimation Setting	Filter Blocks Used
4	CS19, CS55
8	CS11, CS15, CS55
10	CS11, CS139
16	CS7, CS11, CS15, CS55
20	CS7, CS11, CS139
32	CS7, CS7, CS11, CS15, CS55

Table 9. Filter Coefficient Details

Filter Coefficient Set (Decimation Factor of Filter)
CS7 (2)		CS11 (2)		CS15 (2)		CS19 (2)		CS55 (2)		CS139 (5)
–65	–65	109	109	–327	–327	22	22	–37	–37	–5	–5
0	0	0	0	0	0	0	0	0	0	–9	–9
577	577	–837	–837	2231	2231	–174	–174	118	118	–9	–9
1024		0	0	0	0	0	0	0	0	–5	–5
		4824	4824	–8881	–8881	744	744	–291	–291	0	0
		8192		0	0	0	0	0	0	20	20
				39742	39742	–2429	–2429	612	612	33	33
				65536		0	0	0	0	33	33
						10029	10029	–1159	–1159	21	21
						16384		0	0	0	0
								2031	2031	–54	–54
								0	0	–88	–88
								–3356	–3356	–89	–89
								0	0	–56	–56
								5308	5308	0	0
								0	0	119	119
								–8140	–8140	196	196
								0	0	199	199
								12284	12284	125	125
								0	0	0	0
								–18628	–18628	–234	–234
								0	0	–385	–385
								29455	29455	–393	–393
								0	0	–248	–248
								–53191	–53191	0	0
								0	0	422	422
								166059	166059	696	696
								262144		711	711
										450	450
										0	0
										–711	–711
										–1176	–1176
										–1206	–1206
										–766	–766
										0	0
										1139	1139
										1893	1893
										1949	1949
										1244	1244
										0	0
										–1760	–1760
										–2940	–2940
										–3044	–3044
										–1955	–1955
										0	0
										2656	2656
										4472	4472
										4671	4671
										3026	3026
										0	0
										–3993	–3993
										–6802	–6802
										–7196	–7196
										–4730	–4730
										0	0
										6159	6159
										10707	10707
										11593	11593
										7825	7825
										0	0
										–10423	–10423
										–18932	–18932
										–21629	–21629
										–15618	–15618
										0	0
										24448	24448
										52645	52645
										78958	78958
										97758	97758
										104858

7.3.6.4 DDC Output Data

The DDC output data consist of 15-bit complex data plus the two over-range threshold-detection control bits. The following table lists the data format:

	16-BIT OUTPUT WORD
CHANNEL	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I	DDC Output In-Phase (I) 15 bit															OR_T0
Q	DDC Output Quadrature (Q) 15 bit															OR_T1

7.3.6.5 Decimation Settings

7.3.6.5.1 Decimation Factor

The decimation setting is adjustable over the following settings:

Bypass — no decimation
Decimate-by-4
Decimate-by-8
Decimate-by-10
Decimate-by-16
Decimate-by-20
Decimate-by-32

NOTE

Because the output format is complex I+Q, the effective output bandwidth is approximately two-times the value for a real output with the same decimation factor.

7.3.6.5.2 DDC Gain Boost

The DDC gain boost (register 0x200, bit 4) provides additional gain through the DDC block. With a setting of 1 the final filter has 6.02-dB gain. With a setting of 0, the final filter has a 0-dB gain. This setting is recommended when the NCO is set near DC.

7.3.7 Data Outputs

The data outputs (DSx±) are very high-speed differential outputs and conform to the JESD204B JEDEC standard. A CML (current-mode logic)-type output driver is used for each output pair. Output pre-emphasis is adjustable to compensate for longer PCB-trace lengths.

7.3.7.1 The Digital Outputs

The ADC12J1600 and ADC12J2700 output data is transmitted on up to eight high-speed serial-data lanes. The output data from the ADC or DDC is formatted to the eight lanes, 8b10b encoded, and serialized. Up to four different serial output rates are possible depending on the decimation mode setting: 1x, 1.25x, 2x, and 2.5x. In 1x mode, the output serializers run at the same bit rate as the frequency of the applied DEVCLK. In 1.25x mode, the output serializers run at a bit rate that is 1.25-times that of the applied DEVCLK, and so on. For example, for a 1.6-GHz input DEVCLK, the output rates are 1.6 Gbps in 1x mode, 2 Gbps in 1.25x mode, 3.2 Gbps in 2x mode and 4 Gbps in 2.5x mode.

7.3.7.2 JESD204B Interface Features and Settings

7.3.7.2.1 Scrambler Enable

Scrambling randomizes the 8b10b encoded data, spreading the frequency content of the data interface. This reduces the peak EMI energy at any given frequency reducing the possibility of feedback to the device inputs impacting performance. The scrambler is disabled by default and is enabled via SCR (register 0x201, bit 7).

7.3.7.2.2 Frames Per Multi-Frame (K-1)

The frames per multi-frame (K) setting can be adjusted within constraints that are dependant on the selected decimation (D) and serial rate (DDR) settings. The K-minus-1 (KM1) register setting (register 0x201, bits 6:2) must be one less than the desired K setting.

7.3.7.2.3 DDR

The serial rate can be either 1ƒ_(CLK) (DDR = 0) or 2ƒ_(CLK) (DDR = 1).

7.3.7.2.4 JESD Enable

The JESD interface must be disabled (JESD_EN is set to 0) while any of the other JESD parameters are changed. While JESD_EN is set 0 the block is held in reset and the serializers are powered down. The clocks for this section are also gated off to further save power. When the parameters have been set as desired the JESD block can be enabled (JESD_EN is set to 1).

7.3.7.2.5 JESD Test Modes

Several different JESD204B test modes are available to assist in link verification and debugging. The list of modes follows.

NOTE

PRBS test signals are output directly, without 8b10b encoding.

Normal operation
PRBS7 test mode
PRBS15 test mode
PRBS23 test mode
Ramp test mode
Short or long transport-layer test mode
D21.5 test mode
K28.5 test mode
Repeated ILA test mode
Modified RPAT test mode
Serial-outputs differential 0 test mode
Serial-outputs differential 1 test mode

7.3.7.2.6 Configurable Pre-Emphasis

The high-speed serial-output drivers incorporate a configurable pre-emphasis feature. This feature allows the output drive waveform to be optimized for different PCB materials and signal transmission distances. The pre-emphasis setting is adjusted through the serializer pre-emphasis setting in register 0x040, bits 3 to 0. The default setting is 4d. Higher values will increase the pre-emphasis to compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. The pre-emphasis setting should be adjusted to optimize the eye-opening for the hardware configuration and line rates needed.

7.3.7.2.7 Serial Output-Data Formatting

Output data is generated by the DDC then formatted according to the selected decimation and output rate settings. When less than the maximum of eight lanes are active, lanes are disabled beginning with the highest numerical lanes. For example when only two lanes are active, lanes 0 and 1 are active, while all higher lanes are inactive.

Table 10. Parameter Definitions

PARAMETER	DESCRIPTION	USER CONFIGURED OR DERIVED	STANDARD JESD204B LINK PARAMETER
D	Decimation factor, determined by DMODE register	User	No
DDR	Serial line rate: 1 = DDR rate (2x), 0 = SDR rate (1x)	User	No
P54	Enable 5/4 PLL to increase line rate by 1.25x.	User	No
	0 = no PLL (1x), 1 = enable PLL (1.25x)
K	Number of frames per multiframe	User	Yes
N	Bits per sample (before adding control bits and tails bits)	Derived	Yes
CS	Control bits per sample	Derived	Yes
N’	Bits per sample (after adding control bits and tail bits). Must be a multiple of 4.	Derived	Yes
L	Number of serial lanes	Derived	Yes
F	Number of octets (bytes) per frame (per lane)	Derived	Yes
M	Number of (logical) converters	Derived	Yes
S	Number of samples per converter per frame	Derived	Yes
CF	Number of control words per frame	Derived	Yes
HD	1=High density mode (samples may be broken across lanes), 0 = normal mode (samples may not be broken across lanes)	Derived	Yes
KS	Legal adjustment step for K, to ensure that the multi-frame clock is a sub-harmonic of other internal clocks	Derived	No

Table 11. Serial Link Parameters⁽¹⁾

USER SPECIFIED PARAMETERS			DERIVED PARAMETERS								OTHER INFORMATION
DECIMATION FACTOR (D)	DDR	P54	N	CS	N’	L	F	M	S	KS	LEGAL K RANGE	BIT RATE / ADC CLOCK⁽²⁾
1	1	0	12	0	12	8	8	8	5	2	4-32	2x
4	1	0	15	1	16	5	4	2	5	4	8-32	2x
4	1	1	15	1	16	4	2	2	2	2	10-32	2.5x
8	0	0	15	1	16	5	4	2	5	2	6-32	1x
8	0	1	15	1	16	4	2	2	2	1	9-32	1.25x
8	1	0	15	1	16	3	8	2	5	2	4-32	2x
8	1	1	15	1	16	2	2	2	1	2	10-32	2.5x
10	0	0	15	1	16	4	2	2	2	4	12-32	1x
10	1	0	15	1	16	2	2	2	1	8	16-32	2x
16	0	0	15	1	16	3	8	2	5	1	3-32	1x
16	0	1	15	1	16	2	2	2	1	1	9-32	1.25x
16	1	0	15	1	16	2	16	2	5	1	2-32	2x
16	1	1	15	1	16	1	4	2	1	1	5-32	2.5x
20	0	0	15	1	16	2	2	2	1	4	12-32	1x
20	1	0	15	1	16	1	4	2	1	4	8-32	2x
32	0	0	15	1	16	2	16	2	5	1	2-32	1x
32	0	1	15	1	16	1	4	2	1	1	5-32	1.25x
32	1	0	15	1	16	1	32	2	5	1	1-32	2x

(1) In all modes: HD = 0 and CF = 0

(2) x = times (for example, 2x = 2-times)

Output data is formatted in a specific optimized fashion for each decimation and DDR setting combination. For bypass mode (decimation = 1) the 12-bit offset binary values are mapped to the 8-bit characters. For the DDC mode the 16-bit values (15-bit complex data plus 1 bit OR_Tn) are mapped to the 8-bit characters. The following tables list the specific mapping formats. In all mappings the T or tail bits are 0 (zero).

Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8

	TIME →
CHAR NUMBER	0	1		2	3	4		5	6	7
Lane 0	C0S0		C0S1		C0S2		C0S3		C0S4		T
Lane 1	C1S0		C1S1		C1S2		C1S3		C1S4		T
Lane 2	C2S0		C2S1		C2S2		C2S3		C2S4		T
Lane 3	C3S0		C3S1		C3S2		C3S3		C3S4		T
Lane 4	C4S0		C4S1		C4S2		C4S3		C4S4		T
Lane 5	C5S0		C5S1		C5S2		C5S3		C5S4		T
Lane 6	C6S0		C6S1		C6S2		C6S3		C6S4		T
Lane 7	C7S0		C7S1		C7S2		C7S3		C7S4		T
	Frame n

Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters

	TIME →
CHAR NUMBER	0	1		2	3	4		5	6	7
Lane 0	S0		S8		S16		S24		S32		T
Lane 1	S1		S9		S17		S25		S33		T
Lane 2	S2		S10		S18		S26		S34		T
Lane 3	S3		S11		S19		S27		S35		T
Lane 4	S4		S12		S20		S28		S36		T
Lane 5	S5		S13		S21		S29		S37		T
Lane 6	S6		S14		S22		S30		S38		T
Lane 7	S7		S15		S23		S31		S39		T
	Frame n

Table 14. Decimate-by-4, DDR = 1, P54 = 0, LMF = 5,2,4

	TIME →
CHAR NUMBER	0	1	2	3
Lane 0	I₀		I₁
Lane 1	I₂		I₃
Lane 2	I₄		Q₀
Lane 3	Q₁		Q₂
Lane 4	Q₃		Q₄
	Frame n

Table 15. Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5
Lane 0	I₀		I₂		I₄
Lane 1	I₁		I₃		I₅
Lane 2	Q₀		Q₂		Q₄
Lane 3	Q₁		Q₃		Q₅
	Frame n		Frame n + 1		Frame n + 2

Table 16. Decimate-by-8, DDR = 0, P54 = 0, LMF = 5,2,4

	TIME →
CHAR NUMBER	0	1	2	3
Lane 0	I₀		I₁
Lane 1	I₂		I₃
Lane 2	I₄		Q₀
Lane 3	Q₁		Q₂
Lane 4	Q₃		Q₄
	Frame n

Table 17. Decimate-by-8, DDR = 0, P54 = 1, LMF = 4,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5
Lane 0	I₀		I₂		I₄
Lane 1	I₁		I₃		I₅
Lane 2	Q₀		Q₂		Q₄
Lane 3	Q₁		Q₃		Q₅
	Frame n		Frame n + 1		Frame n + 2

Table 18. Decimate-by-8, DDR = 1, P54 = 0, LMF = 3,2,8

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		I₁		I₂		I₃
Lane 1	I₄		Q₀		Q₁		Q₂
Lane 2	Q₃		Q₄		T		T
	Frame n

Table 19. Decimate-by-8, DDR = 1, P54=1, LMF = 2,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5
Lane 0	I₀		I₁		I₂
Lane 1	Q₀		Q₁		Q₂
	Frame n		Frame n + 1		Frame n + 2

Table 20. Decimate-by-10, DDR = 0, P54 = 0, LMF = 4,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		I₂		I₄		I₆
Lane 1	I₁		I₃		I₅		I₇
Lane 2	Q₀		Q₂		Q₄		Q₆
Lane 3	Q₁		Q₃		Q₅		Q₇
	Frame n		Frame n + 1		Frame n + 2		Frame n + 3

Table 21. Decimate-by-10, DDR = 1, P54 = 0, LMF = 2,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		I₁		I₂		I₃
Lane 1	Q₀		Q₁		Q₂		Q₃
	Frame n		Frame n + 1		Frame n + 2		Frame n+3

Table 22. Decimate-by-16, DDR = 0, P54 = 0, LMF = 3,2,8

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		I₁		I₂		I₃
Lane 1	I₄		Q₀		Q₁		Q₂
Lane 2	Q₃		Q₄		T		T
	Frame n

Table 23. Decimate-by-16, DDR = 0, P54 = 1, LMF = 2,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5
Lane 0	I₀		I₁		I₂
Lane 1	Q₀		Q₁		Q₂
	Frame n		Frame n + 1		Frame n + 2

Table 24. Decimate-by-16, DDR = 1, P54 = 0, LMF = 2,2,16

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Lane 0	I₀		I₁		I₂		I₃		I₄		Q₀		Q₁		Q₂
Lane 1	Q₃		Q₄		T		T		T		T		T		T
	Frame n

Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7	8	9	10	11
Lane 0	I₀		Q₀		I₁		Q₁		I₂		Q₂
	Frame n				Frame n + 1				Frame n + 2

Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		I₁		I₂		I₃
Lane 1	Q₀		Q₁		Q₂		Q₃
	Frame n		Frame n + 1		Frame n + 2		Frame n + 3

Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7
Lane 0	I₀		Q₀		I₁		Q₁
	Frame n				Frame n + 1

Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Lane 0	I₀		I₁		I₂		I₃		I₄		Q₀		Q₁		Q₂
Lane 1	Q₃		Q₄		T		T		T		T		T		T
	Frame n

Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7	8	9	10	11
Lane 0	I₀		Q₀		I₁		Q₁		I₂		Q₂
	Frame n				Frame n + 1				Frame n + 2

Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32

	TIME →
CHAR NUMBER	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
Lane 0	I₀		I₁		I₂		I₃		I₄		Q₀		Q₁		Q₂		Q₃		Q₄		T		T		T		T		T		T
	Frame n

The formatted data is 8b10b encoded and output on the serial lanes. The 8b10b encoding provides a number of specific benefits, including:

Standard encoding format. Therefore the IP is readily available in off-the-shelf FPGAs and ASIC building blocks.
Inherent DC balance allows AC coupling of lanes with small on-chip capacitors
Inherent error checking

7.3.7.2.8 JESD204B Synchronization Features

The JESD204B standard defines methods for synchronization and deterministic latency in a multi-converter system. These devices are a JESD204B Subclass 1 device and conforms to the various aspects of link operation as described in section 5.3.3 of the JESD204B standard. The specific signals used to achieve link operation are described briefly in the following sections.

7.3.7.2.9 SYSREF

The SYSREF is a periodic signal which is sampled by the device clock, and is used to align the boundary of the local multi-frame clock inside the data converter. SYSREF

is required to be a sub-harmonic of the LMFC internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency as determined by the selected DDC decimation and frames per multi-frame settings. This clock is typically in the range of 10 MHz to 300 MHz. See the Multiple ADC Synchronization section for more details on SYSREF timing requirements.

7.3.7.2.10 SYNC~

SYNC~ is asserted by the receiver to initiate a synchronization event.

Single ended and differential SYNC~ inputs are provided. The SYNC_DIFFSEL bit (register 0x202, bit 6) is used to select which input is used. Using the single ended SYNC~ input is recommended, as this frees the differential SYNC~/TMST input pair for use in the Time Stamp function. To assert SYNC~, a logic low is applied. To deassert SYNC~ a logic high is applied.

7.3.7.2.11 Time Stamp

When configured through the TIME_STAMP_EN register setting (register 0x050, bit 5), the SYNC~ differential input (pins 22 and 23) can be used as a time-stamp input. The time-stamp feature enables the user to capture the timing of an external trigger event relative to the sampled signal. When enabled, the LSB of the 12-bit ADC digital output captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger must be applied to the differential SYNC~/TMST inputs. The trigger can be asynchronous to the ADC sampling clock and is sampled at approximately the same time as the analog input.

7.3.7.2.12 Code-Group Synchronization

Code-group synchronization is achieved using the following process:

The receiver issues a synchronization request through the SYNC~ input
The transmitter issues a stream of K28.5 symbols
The receiver synchronizes and waits for correct reception of at least 4 consecutive K symbols
The receiver deactivates the synchronization request
Upon detecting that the receiver has deactivated the SYNC~ pin, the transmitter continues emitting K symbols until the next LMFC boundary (or optionally a later LMFC boundary)
On the first frame following the selected LMFC boundary the transmitters emit an initial lane-alignment sequence

The initial-lane alignment sequence transmitted by the ADC device is defined in additional detail in JESD204B section 5.3.3.5.

7.3.7.2.13 Multiple ADC Synchronization

The second function for the SYSREF input is to facilitate the precise synchronization of multiple ADCs in a system.

One key challenge is to ensure that this synchronization works is to ensure that the SYSREF inputs are repeatedly captured by the input CLK. Two key elements must occur for the SYSREF inputs to be captured. First, the SYSREF input must be created so that it is synchronous to the input DEVCLK, be an integer sub-harmonic of the multi-frame (K × t_(FRAME)) and a repeatable and fixed-phase offset. When this constraint is achieved, repeatedly capturing SYSREF is easier. To further ease this task, the SYSREF signal is routed through a user-adjustable delay which eases the timing requirements with respect to the input DEVCLK signal. The SYSREF delay RDEL is adjusted through bits 3 through 0 in register 0x032.

As long as the SYSREF signal has a fixed timing relationship to DEVCLK, the internal delay can be used to maximize the setup and hold times between the internally delayed SYSREF and the internal DEVCLK signal. These timing relationships are listed in the Timing Requirements table. To find the proper delay setting, the RDEL value is adjusted from minimum to maximum while applying SYSREF and monitoring the SysRefDet and Dirty Capture detect bits. The SysRefDet bit is set whenever a rising edge of SYSREF is detected. The Dirty Capture bit is set whenever the setup or hold time between DEVCLK and the delayed SYSREF is insufficient. The SysRefDetClr bit is used to clear the SysRefDet bit. The Clear Dirty Capture bit is used to clear that bit.

This procedure should be followed to determine the range of delay settings where a clean SYSREF capture is achieved. The delay value at the center of the clean capture range must be loaded as the final RDEL setting. Table 31 lists a summary of the control bits that are used and the monitor bits that are read.

Table 31. SYSREF Capture Control and Status

BIT NAME	REGISTER ADDRESS	REGISTER BIT	FUNCTION
RDEL	0x032	3:0	Adjust relative delay between DEVCLK and SYSREF
SysRefDet	0x031	7	Detect if a SYSREF rising edge has been captured (not self clearing)
Dirty Capture	0x031	6	Detect if SYSREF rising edge capture failed setup/hold (not self clearing)
SysRefDetClr	0x030	5	Clear SYSREF detection bit
Clear Dirty Capture	0x030	4	Clear Dirty Capture detection bit
SysRef_Rcvr_En	0x030	7	Enable SYSREF receiver. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information.
SysRef_Pr_En	0x030	6	Enable SYSREF processing. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information.

One final aspect of multi-device synchronization relates to phase alignment of the NCO phase accumulators when DDC modes are enabled. The NCO phase accumulators are reset during the ILA phase of link startup which means that for multiple ADCs to have NCO phase alignment, all links must be enabled in the same LMFC period. Enabling all links in the same LMFC period requires synchronizing the SYNC~ de-assertion across all data receivers in the system, so that all of the SYNC~ signals are released during the same LMFC period. Using large K values and resulting longer LMFC periods will ease this task, at the expense of potentially higher latency in the receiving device.

7.4 Device Functional Modes

7.4.1 DDC Bypass Mode

In DDC bypass mode (decimation = 1) the raw 12 bit data from the ADC is output at the full sampling rate.

7.4.2 DDC Modes

In the DDC modes (decimation > 1) complex (I,Q) data is output at a lower sample rate as determined by the decimation factor (4, 8, 10, 16, 20, and 32).

7.4.3 Calibration

Calibration adjusts the ADC core to optimize the following device parameters:

ADC core linearity
ADC core-to-core offset matching
ADC core-to-core full-scale range matching
ADC core 4-way interleave timing

All calibration processes occur internally. Calibration does not require any external signals to be present and works properly as long as the device is maintained within the values listed in the Recommended Operating Conditions table.

7.4.3.1 Foreground Calibration Mode

In foreground mode the calibration process interrupts normal ADC operation and no output data is available during this time (the output code is forced to a static value). The calibration process should be repeated if the device temperature changes by more than 20ºC to ensure rated performance is maintained. Foreground calibration is initiated by setting the CAL_SFT bit (register 0x050, bit 3) which is self clearing. The foreground calibration process finishes within t_(CAL) number of DEVCLK cycles. The process occurs somewhat longer when the timing calibration mode is enabled.

NOTE

Initiating a foreground calibration asynchronously resets the calibration control logic and may glitch internal device clocks. Therefore after setting the CAL_SFT bit clearing and then setting JESD_EN is necessary. If resetting the JESD204B link is undesirable for system reasons, background calibration mode may be preferred.

7.4.3.2 Background Calibration Mode

In background mode an additional ADC core is powered-up for a total of 5 ADC cores. At any given time, one core is off-line and not used for data conversion. This core is calibrated in the background and then placed on-line simultaneous with another core going off-line for calibration. This process operates continuously without interrupting data flow in the application and ensures that all cores are optimized in performance regardless of any changes of temperature. The background calibration cycle rate is fixed and is not adjustable by the user.

Because of the additional circuitry active in background calibration mode, a slight degradation in performance occurs in comparison to foreground calibration mode at a fixed temperature. As a result of this degradation, using foreground calibration mode is recommended if the expected change in operating temperature is <30°C. Using background calibration mode is recommended if the expected change in operating temperature is >30°C. The exact difference in performance is dependent on the DEVCLK (sampling clock) frequency, and the analog input signal frequency and amplitude. For this reason, device and system performance should be evaluated using both calibration modes before finalizing the choice of calibration mode.

To enable the background calibration feature, set the CAL_BCK bit (register 0x057, bit 0) and the CAL_CONT bit (register 0x057, bit 1). The value written to the register 0x057 to enable background calibration is therefore 0x013h. After writing this value to register 0x057, set the CAL_SFT bit in register 0x050 to perform the one-time foreground calibration to begin the process.

NOTE

The ADC offset-adjust feature has no effect when background calibration mode is enabled.

7.4.4 Timing Calibration Mode

The timing calibration process optimizes the matching of sample timing for the 4 internally interleaved converters. This process minimize the presence of any timing related interleaving spurs in the captured spectrum. The timing calibration feature is disabled by default, but using this feature is highly recommended. To enable timing calibration, set the T_AUTO bit (register 0x066, bit 0). When this bit is set, the timing calibration performs each time the CAL_SFT bit is set.

Table 32. Calibration Cycle Timing for Different Calibration Modes and Options

CAL_CONT, CAL_BCK	T_AUTO	LOW_SIG_EN	INITIAL ONE-TIME CALIBRATION CAL_SFT 0 → 1 (t_DEVCLK)	BACKGROUND CALIBRATION CYCLE⁽¹⁾ (ALL CORES) (t_DEVCLK)
0	0	0	102 E+6	N/A
0	0	1	64 E+6	N/A
0	1	0	227 E+6	N/A
0	1	1	189 E+6	N/A
1	0	0	127.5 E+6	816 E+6
1	0	1	80 E+6	512 E+6
1	1	0	283.75 E+6	816 E+6
1	1	1	236.25 E+6	512 E+6

(1) N/A = not applicable

7.4.5 Test-Pattern Modes

A number of device test modes are available. These modes insert known patterns of information into the device data path for assistance with system debug, development, or characterization.

7.4.5.1 ADC Test-Pattern Mode

The 12-bit ADC core has a built-in test-pattern generator. This mode is helpful for verifying the full data link from the ADC to the data receiver when in DDC bypass mode. When the test-pattern mode is enabled, the ADC output data is replaced by a pattern that repeats every two frames. The data sequence is is shown in Table 33 (shown for default settings with foreground calibration mode).

Table 33. ADC Test Pattern⁽¹⁾

LANE (CONVERTER ID)	SAMPLE NUMBER (SID)
	0	1	2	3	4	5	6	7	8	9
0	0x000	0xFFF	0x000	0xFFF	0x000	0xFFF	0x000	0xFFF	0x000	0xFFF
1	0x008	0xFF7	0x008	0xFF7	0x008	0xFF7	0x008	0xFF7	0x008	0xFF7
2	0x010	0xFEF	0x010	0xFEF	0x010	0xFEF	0x010	0xFEF	0x010	0xFEF
3	0x020	0xFDF	0x020	0xFDF	0x020	0xFDF	0x020	0xFDF	0x020	0xFDF
4	0x040	0xFBF	0x040	0xFBF	0x040	0xFBF	0x040	0xFBF	0x040	0xFBF
5	0x100	0xEFF	0x100	0xEFF	0x100	0xEFF	0x100	0xEFF	0x100	0xEFF
6	0x200	0xDFF	0x200	0xDFF	0x200	0xDFF	0x200	0xDFF	0x200	0xDFF
7	0x400	0xBFF	0x400	0xBFF	0x400	0xBFF	0x400	0xBFF	0x400	0xBFF

(1) When background-calibration mode is enabled, the pattern values are dynamic because the internal converter banks are output on different lanes during the calibration bank-switching process. Each converter bank has dedicated pattern values as listed in Table 34.

Table 34. ADC Bank Pattern Values

BANK	LOCATION	LOW VALUE	HIGH VALUE
0	Lane n	0x000	0xFFF
0	Lane n+4	0x040	0xFBF
1	Lane n	0x004	0xFFE
1	Lane n+4	0x080	0xF7F
2	Lane n	0x008	0xFF7
2	Lane n+4	0x100	0xEFF
3	Lane n	0x010	0xFEF
3	Lane n+4	0x200	0xDFF
4	Lane n	0x020	0xFDF
4	Lane n+4	0x400	0xBFF

7.4.5.2 Serializer Test-Mode Details

Test modes are enabled by setting the appropriate configuration of the JESD204B_TEST setting (Register 0x202, Bits 3:0). Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs are powered up based on the configuration decimation and DDR settings. The test modes should only be enabled while the JESD204B link is disabled.

ADC12J1600 ADC12J2700 JESD204_Test_Modes_Flow.gif

Figure 66. Test-Mode Insertion Points

7.4.5.3 PRBS Test Modes

The PRBS test modes bypass the 8B10B encoder. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can self-synchronize to the bit pattern and therefore the initial phase of the pattern is not defined.

The sequences are defined by a recursive equation. For example, the PRBS7 sequence is defined as shown in Equation 9.

Equation 9. y[n] = y[n – 6]^{y[n – 7]}

where

Bit n is the XOR of bit [n – 6] and bit [n – 7] which are previously transmitted bits

Table 35. PBRS Mode Equations

PRBS TEST MODE	SEQUENCE	SEQUENCE LENGTH (bits)
PRBS7	y[n] = y[n – 6]^{y[n – 7]}	127
PRBS15	y[n] = y[n – 14]^{y[n – 15]}	32767
PRBS23	y[n] = y[n – 18]^{y[n – 23]}	8388607

The initial phase of the pattern is unique for each lane.

7.4.5.4 Ramp Test Mode

In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that increments from 0x00 to 0xFF and repeats.

7.4.5.5 Short and Long-Transport Test Mode

The short-transport test mode is available when the device is operated in DDC bypass mode (decimation = 1). The short transport pattern has a length of one frame. Table 36 lists the formula followed by each sample of the pattern.

Table 36. Short Transport Test Pattern Definition

BIT
11	10	9	8	7	6	5	4	3	2	1	0
~LID				LID				SID+1

LID is the lane ID (0 to 7) and SID is the sample number within the frame (0 to 4). The entire pattern has a length of one frame and is listed in Table 37.

Table 37. Short Transport Test Pattern

LANE (CONVERTER ID)	SAMPLE NUMBER (SID)
	0	1	2	3	4
0	0xF01	0xF02	0xF03	0xF04	0xF05
1	0xE11	0xE12	0xE13	0xE14	0xE15
2	0xD21	0xD22	0xD23	0xD24	0xD25
3	0xC31	0xC32	0xC33	0xC34	0xC35
4	0xB41	0xB42	0xB43	0xB44	0xB45
5	0xA51	0xA52	0xA53	0xA54	0xA55
6	0x961	0x962	0x963	0x964	0x965
7	0x871	0x872	0x873	0x874	0x875

The long-transport test mode is available in all DDC modes (decimation > 1). Patterns are generated in accordance with the JESD204B standard and are different for each output format.

Table 38 lists one example of the long transport test pattern:

Table 38. Long Transport Test Pattern - Decimate-by-4, DDR = 1, P54 = 1, K=10

	TIME →
CHAR NO.	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21
Lane 0	0x0003		0x0002		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x0003
Lane 1	0x0002		0x0005		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x0002
Lane 2	0x0004		0x0002		0x8001		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x0004
Lane 3	0x0004		0x0004		0x8000		0x8001		0x8000		0x8000		0x8000		0x8000		0x8000		0x8000		0x0004
	Frame n		Frame n + 1		Frame n + 2		Frame n + 3		Frame n + 4		Frame n + 5		Frame n + 6		Frame n + 7		Frame n + 8		Frame n + 9		Frame n + 10

If multiple devices are all programmed to the transport layer test mode (while JESD_EN = 0), then JESD_EN is set to 1, and then SYSREF is used to align the LMFC of the devices, the patterns will be aligned to the SYSREF event (within the skew budget of JESD204B). For more details see JESD204B, section 5.1.6.3.

7.4.5.6 D21.5 Test Mode

In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s).

7.4.5.7 K28.5 Test Mode

In this test mode, the controller transmits a continuous stream of K28.5 characters.

7.4.5.8 Repeated ILA Test Mode

In this test mode, the JESD204B link layer operates normally with one exception: when the ILA sequence completes, the sequence repeats indefinitely. Whenever the receiver issues a synchronization request, the transmitter will initiate code group synchronization. Upon completion of code group synchronization, the transmitter will repeatedly transmit the ILA sequence. If there is no active code group synchronization request at the moment the transmitter enters the test mode, the transmitter will behave as if it received one.

7.4.5.9 Modified RPAT Test Mode

A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white spectral content for JESD204B compliance and jitter testing. Table 39 lists the pattern before and after 8b10b encoding.

Table 39. Modified RPAT Pattern Values

OCTET NUMBER	Dx.y NOTATION	8-BIT INPUT TO 8b10b ENCODER	20b OUTPUT OF 8b10b ENCODER (2 CHARACTERS)
0	D30.5	0xBE	0x86BA6
1	D23.6	0xD7	0x86BA6
2	D3.1	0x23	0xC6475
3	D7.2	0x47	0xC6475
4	D11.3	0x6B	0xD0E8D
5	D15.4	0x8F	0xD0E8D
6	D19.5	0xB3	0xCA8B4
7	D20.0	0x14	0xCA8B4
8	D30.2	0x5E	0x7949E
9	D27.7	0xFB	0x7949E
10	D21.1	0x35	0xAA665
11	D25.2	0x59	0xAA665

7.5 Programming

7.5.1 Using the Serial Interface

The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin.

SCS

This signal must be asserted low to access a register through the serial interface. Setup and hold times with respect to the SCLK must be observed.

SCLK

Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.

SDI

Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write (R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and hold times with respect to the SCLK must be observed (see Figure 2).

SDO

The SDO signal provides the output data requested by a read command. This output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles.

Each register access consists of 24 bits, as shown in Figure 2. The first bit is high for a read and low for a write.

The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in Figure 67.

ADC12J1600 ADC12J2700 serial_protocol_standard_slas989.gif

Figure 67. Serial Interface Protocol - Single Read / Write

7.5.1.1 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_STATIC bit (register 010h, bit 0). The streaming mode transaction details are shown in Figure 68.

ADC12J1600 ADC12J2700 serial_protocol_streaming_slas989.gif

Figure 68. Serial Interface Protocol - Streaming Read / Write

See the Register Map section for detailed information regarding the registers.

NOTE

The serial interface must not be accessed during calibration of the ADC. Accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. Writing or reading the serial registers also reduces dynamic performance of the ADC for the duration of the register access time.

7.6 Register Map

Several groups of registers provide control and configuration options for this device. Each following register description also shows the power-on reset (POR) state of each control bit.

NOTE

All multi-byte registers are arranged in little-endian format (the least-significant byte is stored at the lowest address) unless explicitly stated otherwise.

7.6.1 Memory Map

Address	Reset	Type	Register
Standard SPI-3.0 (0x000 to 0x00F)
0x000	0x3C	R/W	Configuration A Register
0x001	0x00	R	Configuration B Register
0x002	0x00	R/W	Device Configuration Register
0x003	0x03	R	Chip Type Register
0x004-0x005	Undefined	R	RESERVED
0x006	0x13	R	Chip Version Register
0x007-0x00B	Undefined	R	RESERVED
0x00C-0x00D	0x0451	R	Vendor Identification Register
0x00E-0x00F	Undefined	R	RESERVED
User SPI Configuration (0x010 to 0x01F)
0x010	0x00	R/W	User SPI Configuration Register
0x011-0x01F	Undefined	R	RESERVED
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
0x020	0x9D	R/W	RESERVED
0x021	0x00	R/W	Power-On Reset Register
0x022	0x40	R/W	I/O Gain 0 Register
0x023	0x00	R/W	I/O Gain 1 Register
0x024	0x00	R/W	RESERVED
0x025	0x40	R/W	I/O Offset 0 Register
0x026	0x00	R/W	I/O Offset 1 Register
0x027	0x06	R/W	RESERVED
0x028	0xBA	R/W	RESERVED
0x029	0xD4	R/W	RESERVED
0x02A	0xEA	R/W	RESERVED
0x02B-0x02F	Undefined	R	RESERVED
Clock (0x030 to 0x03F)
0x030	0xC0	R/W	Clock Generator Control 0 Register
0x031	0x07	R	Clock Generator Status Register
0x032	0x80	R/W	Clock Generator Control 2 Register
0x033	0xC3	R/W	Analog Miscellaneous Register
0x034	0x2F	R/W	Input Clamp Enable Register
0x035	0xDF	R/W	RESERVED
0x036	0x00	R/W	RESERVED
0x037	0x45	R/W	RESERVED
0x038-0x03F	Undefined	R/W	RESERVED
Serializer (0x040 to 0x04F)
0x040	0x04	R/W	Serializer Configuration Register
0x041-0x04F	Undefined	R	RESERVED
ADC Calibration (0x050 to 0x1FF)
0x050	0x06	R/W	Calibration Configuration 0 Register
0x051	0xF4	R/W	Calibration Configuration 1 Register
0x052	0x00	R/W	RESERVED
0x053	0x5C	R/W	RESERVED
0x054	0x1C	R/W	RESERVED
0x055	0x92	R/W	RESERVED
0x056	0x20	R/W	RESERVED
0x057	0x10	R/W	Calibration Background Control Register
0x058	0x00	R/W	ADC Pattern and Over-Range Enable Register
0x059	0x00	R/W	RESERVED
0x05A	0x00	R/W	Calibration Vectors Register
0x05B	Undefined	R	Calibration Status Register
0x05C	0x00	R/W	RESERVED
0x05D-0x05E	Undefined	R/W	RESERVED
0x05F	0x00	R/W	RESERVED
0x060	Undefined	R	RESERVED
0x061	Undefined	R	RESERVED
0x062	Undefined	R	RESERVED
0x063	Undefined	R	RESERVED
0x064	Undefined	R	RESERVED
0x065	Undefined	R	RESERVED
0x066	0x02	R/W	Timing Calibration Register
0x067	0x01	R/W	RESERVED
0x068	Undefined	R	RESERVED
0x069	Undefined	R	RESERVED
0x06A	0x00	R/W	RESERVED
0x06B	0x20	R/W	RESERVED
0x06C-0x1FF	Undefined	R	RESERVED
Digital Down Converter and JESD204B (0x200-0x27F)
0x200	0x10	R/W	Digital Down-Converter (DDC) Control
0x201	0x0F	R/W	JESD204B Control 1
0x202	0x00	R/W	JESD204B Control 2
0x203	0x00	R/W	JESD204B Device ID (DID)
0x204	0x00	R/W	JESD204B Control 3
0x205	Undefined	R/W	JESD204B and System Status Register
0x206	0xF2	R/W	Overrange Threshold 0
0x207	0xAB	R/W	Overrange Threshold 1
0x208	0x00	R/W	Overrange Period
0x209-0x20B	0x00	R/W	RESERVED
0x20C	0x00	R/W	DDC Configuration Preset Mode
0x20D	0x00	R/W	DDC Configuration Preset Select
0x20E-0x20F	0x0000	R/W	Rational NCO Reference Divisor
PRESET 0
0x210-0x213	0xC0000000	R/W	NCO Frequency (Preset 0)
0x214-0x215	0x0000	R/W	NCO Phase (Preset 0)
0x216	0xFF	R/W	DDC Delay (Preset 0)
0x217	0x00	R/W	RESERVED
PRESET 1
0x218-0x21B	0xC0000000	R/W	NCO Frequency (Preset 1)
0x21C-0x21D	0x0000	R/W	NCO Phase (Preset 1)
0x21E	0xFF	R/W	DDC Delay (Preset 1)
0x21F	0x00	R/W	RESERVED
PRESET 2
0x220-0x223	0xC0000000	R/W	NCO Frequency (Preset 2)
0x224-0x225	0x0000	R/W	NCO Phase (Preset 2)
0x226	0xFF	R/W	DDC Delay (Preset 2)
0x227	0x00	R/W	RESERVED
PRESET 3
0x228-0x22B	0xC0000000	R/W	NCO Frequency (Preset 3)
0x22C-0x22D	0x0000	R/W	NCO Phase (Preset 3)
0x22E	0xFF	R/W	DDC Delay (Preset 3)
0x22F	0x00	R/W	RESERVED
PRESET 4
0x230-0x233	0xC0000000	R/W	NCO Frequency (Preset 4)
0x234-0x235	0x0000	R/W	NCO Phase (Preset 4)
0x236	0xFF	R/W	DDC Delay (Preset 4)
0x237	0x00	R/W	RESERVED
PRESET 5
0x238-0x23B	0xC0000000	R/W	NCO Frequency (Preset 5)
0x23C-0x23D	0x0000	R/W	NCO Phase (Preset 5)
0x23E	0xFF	R/W	DDC Delay (Preset 5)
0x23F	0x00	R/W	RESERVED
PRESET 6
0x240-0x243	0xC0000000	R/W	NCO Frequency (Preset 6)
0x244-0x245	0x0000	R/W	NCO Phase (Preset 6)
0x246	0xFF	R/W	DDC Delay (Preset 6)
0x247	0x00	R/W	RESERVED
PRESET 7
0x248-0x24B	0xC0000000	R/W	NCO Frequency (Preset 7)
0x24C-0x24D	0x0000	R/W	NCO Phase (Preset 7)
0x24E	0xFF	R/W	DDC Delay (Preset 7)
0x24F-0x251	0x00	R/W	RESERVED
0x252-0x27F	Undefined	R	RESERVED
Reserved
0x0280-0x7FFF	Undefined	R	RESERVED

7.6.2 Register Descriptions

7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)

Table 40. Standard SPI-3.0 Registers

Address	Reset	Acronym	Register Name	Section
0x000	0x3C	CFGA	Configuration A Register	Go
0x001	0x00	CFGB	Configuration B Register	Go
0x002	0x00	DEVCFG	Device Configuration Register	Go
0x003	0x03	CHIP_TYPE	Chip Type Register	Go
0x004-0x005	0x0000	RESERVED	RESERVED	Go
0x006	0x13	CHIP_VERSION	Chip Version Register	Go
0x007-0x00B	Undefined	RESERVED	RESERVED
0x00C-0x00D	0x0451	VENDOR_ID	Vendor Identification Register	Go
0x00E-0x00F	Undefined	RESERVED	RESERVED

7.6.2.1.1 Configuration A Register (address = 0x000) [reset = 0x3C]

All writes to this register must be a palindrome (for example: bits [3:0] are a mirror image of bits [7:4]). If the data is not a palindrome, the entire write is ignored.

Figure 69. Configuration A Register (CFGA)

7	6	5	4	3	2	1	0
SWRST	RESERVED	ADDR_ASC	RESERVED	RESERVED	ADDR_ASC	RESERVED	SWRST
R/W-0	R/W-0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-0	R/W-0

Table 41. CFGA Field Descriptions

Bit	Field	Type	Reset	Description
7	SWRST	R/W	0	Setting this bit causes all registers to be reset to their default state. This bit is self-clearing.
6	RESERVED	R/W	0
5	ADDR_ASC	R/W	1	This bit is NOT reset by a soft reset (SWRST) 0 : descend – decrement address while streaming (address wraps from 0x0000 to 0x7FFF) 1 : ascend – increment address while streaming (address wraps from 0x7FFF to 0x0000) (default)
4	RESERVED	R/W	1	Always returns 1
3	RESERVED	R/W	1100	Palindrome bits bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, bit 0 = bit 7
2	ADDR_ASC	R/W
1	RESERVED	R/W
0	SWRST	R/W

7.6.2.1.2 Configuration B Register (address = 0x001) [reset = 0x00]

Figure 70. Configuration B Register (CFGB)

7	6	5	4	3	2	1	0
RESERVED
R - 0x00h

Table 42. CFGB Field Descriptions

Bit	Field	Type	Reset	Description
7:0	RESERVED	R	0000 0000

7.6.2.1.3 Device Configuration Register (address = 0x002) [reset = 0x00]

Figure 71. Device Configuration Register (DEVCFG)

7	6	5	4	3	2	1	0
RESERVED						MODE
R/W-000000						R/W-00

Table 43. DEVCFG Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0000 00
1-0	MODE	R/W	00	SPI 3.0 specification has 1 as low power functional mode and 2 as low power fast resume. This chip does not support these modes. 0: Normal Operation – full power and full performance (default) 1: Normal Operation – full power and full performance (default) 2: Power Down – Everything powered down 3: Power Down – Everything powered down

7.6.2.1.4 Chip Type Register (address = 0x003) [reset = 0x03]

Figure 72. Chip Type Register (CHIP_TYPE)

7	6	5	4	3	2	1	0
RESERVED				CHIP_TYPE
R-0000				R-0011

Table 44. CHIP_TYPE Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0000
3-0	CHIP_TYPE	R	0011	Always returns 0x3, indicating that the part is a high speed ADC.

7.6.2.1.5 Chip Version Register (address = 0x006) [reset = 0x13]

Figure 73. Chip Version Register (CHIP_VERSION)

7	6	5	4	3	2	1	0
CHIP_VERSION
R-0001 0011

Table 45. CHIP_VERSION Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CHIP_VERSION	R	0001 0011	Chip version, returns 0x13

7.6.2.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]

Figure 74. Vendor Identification Register (VENDOR_ID)

15	14	13	12	11	10	9	8
VENDOR_ID
R-0x04h

7	6	5	4	3	2	1	0
VENDOR_ID
R-0x51h

Table 46. VENDOR_ID Field Descriptions

Bit	Field	Type	Reset	Description
15-0	VENDOR_ID	R	0x0451h	Always returns 0x0451 (TI Vendor ID)

7.6.2.2 User SPI Configuration (0x010 to 0x01F)

Table 47. User SPI Configuration Registers

Address	Reset	Acronym	Register Name	Section
0x010	0x00	USR0	User SPI Configuration Register	Go
0x011-0x01F	Undefined	RESERVED	RESERVED

7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]

Figure 75. User SPI Configuration Register (USR0)

7	6	5	4	3	2	1	0
RESERVED							ADDR_STATIC
R/W-0000 000							R/W-0

Table 48. USR0 Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000 000
0	ADDR_STATIC	R/W	0	0 : Use ADDR_ASC bit to define what happens to address during streaming (default). 1 : Address stays static throughout streaming operation. Useful for reading/writing calibration vector information at CAL_VECTOR register.

7.6.2.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)

Table 49. General Analog, Bias, Band Gap, and Track and Hold Registers

Address	Reset	Acronym	Register Name	Section
0x020	0x9D	RESERVED	RESERVED
0x021	0x00	POR	Power-On Reset Register	Go
0x022	0x40	IO_GAIN_0	I/O Gain 0 Register	Go
0x023	0x00	IO_GAIN_1	I/O Gain 1 Register	Go
0x024	0x00	RESERVED	RESERVED
0x025	0x40	IO_OFFSET_0	I/O Offset 0 Register	Go
0x026	0x00	IO_OFFSET_1	I/O Offset 1 Register	Go
0x027	0x06	RESERVED	RESERVED
0x028	0xBA	RESERVED	RESERVED
0x029	0xD4	RESERVED	RESERVED
0x02A	0xAA	RESERVED	RESERVED
0x02B-0x02F	Undefined	RESERVED	RESERVED

7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]

Figure 76. Power-On Reset Register (POR)

7	6	5	4	3	2	1	0
RESERVED							SPI_RES
R/W-0000 000							R/W-0

Table 50. POR Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000 000
0	SPI_RES	R/W	0	Reset all digital. Emulates a power on reset (not self-clearing). Write a 0 and then write a 1 to emulate a reset. Transition from 0—>1 initiates reset. Default: 0

7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]

Figure 77. I/O Gain 0 Register (IO_GAIN_0)

7	6	5	4	3	2	1	0
RESERVED	GAIN_FS[14]	GAIN_FS[13]	GAIN_FS[12]	GAIN_FS[11]	GAIN_FS[10]	GAIN_FS[9]	GAIN_FS[8]
R/W-0	R/W-1	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 51. IO_GAIN_0 Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0
6-0	GAIN_FS[14:8]	R/W	100 0000	MSB Bits for GAIN_FS[14:0]. (See the IO_GAIN_1 description in General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F))

7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]

Figure 78. IO_GAIN_1 Register (IO_GAIN_1)

7	6	5	4	3	2	1	0
GAIN_FS[7]	GAIN_FS[6]	GAIN_FS[5]	GAIN_FS[4]	GAIN_FS[3]	GAIN_FS[2]	GAIN_FS[1]	GAIN_FS[0]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 52. IO_GAIN_1 Field Descriptions

Bit	Field	Type	Reset	Description
7-0	GAIN_FS[7:0]	R/W	0000 0000	LSB bits for GAIN_FS[14:0] GAIN_FS[14:0] Value 0x0000 500 mVp-p 0x4000 725 mVp-p (default) 0x7FFF 950 mVp-p

7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]

Figure 79. I/O Offset 0 Register (IO_OFFSET_0)

7	6	5	4	3	2	1	0
RESERVED	OFFSET_FS[14]	OFFSET_FS[13]	OFFSET_FS[12]	OFFSET_FS[11]	OFFSET_FS[10]	OFFSET_FS[9]	OFFSET_FS[8]
R/W-0	R/W-1	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 53. IO_OFFSET_0 Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0
6-0	OFFSET_FS[14:8]	R/W	100 0000	MSB Bits for OFFSET_FS[14:0]. The ADC offset adjust feature has no effect when Background Calibration Mode is enabled. (See IO_OFFSET_1 description in the General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) section).

7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]

Figure 80. I/O Offset 1 Register (IO_OFFSET_1)

7	6	5	4	3	2	1	0
OFFSET_FS[7]	OFFSET_FS[6]	OFFSET_FS[5]	OFFSET_FS[4]	OFFSET_FS[3]	OFFSET_FS[2]	OFFSET_FS[1]	OFFSET_FS[0]
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 54. IO_OFFSET_1 Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OFFSET_FS[7:0]	R/W	0000 0000	LSB bits for OFFSET_FS[14:0]. OFFSET_FS[14:0] adjusts the offset of the entire ADC (all banks are impacted). OFFSET_FS[14:0] Value 0x0000 –28-mV offset 0x4000 no offset (default) 0x7FFF 28-mV offset The ADC offset adjust feature has no effect when Background Calibration Mode is enabled.

7.6.2.4 Clock (0x030 to 0x03F)

Table 55. Clock Registers

Address	Reset	Acronym	Register Name	Section
0x030	0xC0	CLKGEN_0	Clock Generator Control 0 Register	Go
0x031	0x07	CLKGEN_1	Clock Generator Status Register	Go
0x032	0x80	CLKGEN_2	Clock Generator Control 2 Register	Go
0x033	0xC3	ANA_MISC	Analog Miscellaneous Register	Go
0x034	0x2F	IN_CL_EN	Clamp Enable Register	Go
0x035	0xDF	RESERVED	RESERVED
0x036	0x00	RESERVED	RESERVED
0x037	0x45	RESERVED	RESERVED
0x038-0x03F	Undefined	RESERVED	RESERVED

7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]

Figure 81. Clock Generator Control 0 Register (CLKGEN_0)

7	6	5	4	3	2	1	0
SysRef_Rcvr_En	SysRef_Pr_En	SysRefDetClr	Clear Dirty Capture	RESERVED	DC_LVPECL_CLK_en	DC_LVPECL_SYSREF_en	DC_LVPECL_TS_en
R/W-1	R/W-1	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Table 56. CLKGEN_0 Field Descriptions

Bit	Field	Type	Reset	Description
7	SysRef_Rcvr_En	R/W	1	Default: 1 0 : SYSREF receiver is disabled. 1 : SYSREF receiver is enabled (default)
6	SysRef_Pr_En	R/W	1	To power down the SYSREF receiver, clear this bit first, then clear SysRef_Rcvr_En. To power up the SYSREF receiver, set SysRef_Rcvr_En first, then set this bit. Default: 1 0 : SYSREF Processor is disabled. 1 : SYSREF Processor is enabled (default)
5	SysRefDetClr	R/W	0	Default: 0 Write a 1 and then a 0 to clear the SysRefDet status bit.
4	Clear Dirty Capture	R/W	0	Default: 0 Write a 1 and then a 0 to clear the DC status bit.
3	RESERVED	R/W	0	Default: 0
2	DC_LVPECL_CLK_en	R/W	0	Default: 0 Set this bit if DEVCLK is a DC-coupled LVPECL signal through a 50-Ω resistor.
1	DC_LVPECL_SYSREF_en	R/W	0	Default: 0 Set this bit if SYSREF is a DC-coupled LVPECL signal through a 50-Ω resistor.
0	DC_LVPECL_TS_en	R/W	0	Default: 0 Set this bit if TimeStamp is a DC-coupled LVPECL signal through a 50-Ω resistor.

7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]

Figure 82. Clock Generator Status Register (CLKGEN_1)

7	6	5	4	3	2	1	0
SysRefDet	Dirty Capture	RESERVED
R-0	R-0	R-00 0111

Table 57. CLKGEN_1 Field Descriptions

Bit	Field	Type	Reset	Description
7	SysRefDet	R	0	When high, indicates that a SYSREF rising edge was detected. To clear this bit, write SysRefDetClr to 1 and then back to 0.
6	Dirty Capture	R	0	When high, indicates that a SYSREF rising edge occurred very close to the device clock edge, and setup or hold is not ensured (dirty capture). To clear this bit, write CDC to1 and then back to 0. NOTE: When sweeping the timing on SYSREF, it may jump across the clock edge without triggering this bit. The REALIGNED status bit must be used to detect this (see the JESD_STATUS register description in Digital Down Converter and JESD204B (0x200-0x27F))
5-0	RESERVED	R	00 0111	Reserved register. Always returns 000111b

7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]

Figure 83. Clock Generator Control 2 Register (CLKGEN_2)

7	6	5	4	3	2	1	0
RESERVED				RDEL
R/W-1000				R/W-0000

Table 58. CLKGEN_2 Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	1000	Default: 1000b
3-0	RDEL	R/W	0000	Adjusts the delay of the SYSREF input signal with respect to DEVCLK. Each step delays SYSREF by 20 ps (nominal) Default: 0 Range: 0 to 15 decimal

7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]

Figure 84. Analog Miscellaneous Register (ANA_MISC)

7	6	5	4	3	2	1	0
RESERVED					SYNC_DIFF_PD	RESERVED
R/W-1100 0					R/W-0	R/W-11

Table 59. ANA_MISC Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	1100 0
2	SYNC_DIFF_PD	R/W	0	Set this bit to power down the differential SYNC~± inputs for the JESD204B interface. The SYNC~± inputs can also serve as the TimeStamp input receiver for the TimeStamp function. The receiver must be powered up to support the time stamp or differential SYNC~. Default: 0b
1-0	RESERVED	R/W	11	Default: 11b

7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]

Figure 85. Input Clamp Enable Register (IN_CL_EN)

7	6	5	4	3	2	1	0
RESERVED		INPUT_CLAMP_EN	RESERVED
R/W-00		R/W-1	R/W-0 1111

Table 60. IN_CL_EN Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	Default: 00b
5	INPUT_CLAMP_EN	R/W	1	Set this bit to enable the analog input active clamping circuit. Enabled by default. Default: 1b
4-0	RESERVED	R/W	0 1111	Default: 01111b

7.6.2.5 Serializer (0x040 to 0x04F)

Table 61. Serializer Registers

Address	Reset	Acronym	Register Name	Section
0x040	0x04	SER_CFG	Serializer Configuration Register	Go
0x041-0x04F	Undefined	RESERVED	RESERVED

7.6.2.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]

Figure 86. Serializer configuration Register (SER_CFG)

7	6	5	4	3	2	1	0
RESERVED				SERIALIZER PRE-EMPHASIS
R/W-0000				R/W-0100

Table 62. SER_CFG Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000
3-0	SERIALIZER PRE-EMPHASIS	R/W	0100	Control bits for the pre-emphasis strength of the serializer output driver. Pre-emphasis is required to compensate the low pass behavior of the PCB trace. Default: 4d

7.6.2.6 ADC Calibration (0x050 to 0x1FF)

Table 63. ADC Calibration Registers

Address	Reset	Acronym	Register Name	Section
0x050	0x06	CAL_CFG0	Calibration Configuration 0 Register	Go
0x051	0xF4	CAL_CFG1	Calibration Configuration 1 Register	Go
0x052	0x00	RESERVED	RESERVED
0x053	0x5C	RESERVED	RESERVED
0x054	0x1C	RESERVED	RESERVED
0x055	0x92	RESERVED	RESERVED
0x056	0x20	RESERVED	RESERVED
0x057	0x10	CAL_BACK	Calibration Background Control Register	Go
0x058	0x00	ADC_PAT_OVR_EN	ADC Pattern and Over-Range Enable Register	Go
0x059	0x00	RESERVED	RESERVED
0x05A	0x00	CAL_VECTOR	Calibration Vectors Register	Go
0x05B	Undefined	CAL_STAT	Calibration Status Register	Go
0x05C	0x00	RESERVED	RESERVED
0x05D-0x05E	Undefined	RESERVED	RESERVED
0x05F	0x00	RESERVED	RESERVED
0x060	Undefined	RESERVED	RESERVED
0x061	Undefined	RESERVED	RESERVED
0x062	Undefined	RESERVED	RESERVED
0x063	Undefined	RESERVED	RESERVED
0x064	Undefined	RESERVED	RESERVED
0x065	Undefined	RESERVED	RESERVED
0x066	0x02	T_CAL	Timing Calibration Register	Go
0x067	0x01	RESERVED	RESERVED
0x068	Undefined	RESERVED	RESERVED
0x069	Undefined	RESERVED	RESERVED
0x06A	0x00	RESERVED	RESERVED
0x06B	0x20	RESERVED	RESERVED
0x06C-0x1FF	Undefined	RESERVED	RESERVED

7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]

Figure 87. Calibration Configuration 0 Register (CAL_CFG0)

7	6	5	4	3	2	1	0
RESERVED		TIME_STAMP_EN	CALIBRATION_READ_WRITE_EN	CAL_SFT	RESERVED
R/W-00		R/W-0	R/W-0	R/W-0	R/W-110

Table 64. CAL_CFG0 Field Descriptions

Bit	Field	Type	Reset	Description
7-	RESERVED	R/W	00
5	TIME_STAMP_EN	R/W	0	Enables the capture of the external time stamp signal to allow tracking of input signal. Default: 0
4	CALIBRATION_READ_WRITE_EN	R/W	0	Enables the scan register to read or write calibration vectors at register 0x05A. Default: 0
3	CAL_SFT⁽¹⁾	R/W	0	Software calibration bit. Set bit to initiate foreground calibration. This bit is self-clearing. This bit resets the calibration state machine. Most calibration SPI registers are not synchronized to the calibration clock. Changing them may corrupt the calibration state machine. Always set CAL_SFT AFTER making any changes to the calibration registers.
2-0	RESERVED	R/W	110	Default: 110

(1) IMPORTANT NOTE: Setting CAL_SFT can glitch internal state machines. The JESD_EN bit must be cleared and then set after setting CAL_SFT.

7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]

Figure 88. Calibration Configuration 1 Register (CAL_CFG1)

7	6	5	4	3	2	1	0
RESERVED	LOW_SIG_EN			RESERVED
R/W-1	R/W-111			R/W-0100

Table 65. CAL_CFG1 Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	1
6-4	LOW_SIG_EN	R/W	111	Controls signal range optimization for calibration processes. 111: Calibration is optimized for lower amplitude input signals (< –10dBFS). 000: Calibration is optimized for large (-1dBFS) input signals. Default: 111 but recommend 000 for large input signals.
3-0	RESERVED	R/W	0100

7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]

Figure 89. Calibration Background Control Register (CAL_BACK)

7	6	5	4	3	2	1	0
RESERVED						CAL_CONT	CAL_BCK
R/W-0001 00						R/W-0	R/W-0

Table 66. CAL_BACK Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0001 00	Set to 0001 00b
1	CAL_CONT	R/W	0	CAL_CONT is the only calibration register bit that can be modified while background calibration is ongoing. This bit must be set to 0 before modifying any of the other bits. 0 : Pause or stop background calibration sequence. 1 : Start background calibration sequence.
0	CAL_BCK	R/W	0	Background calibration mode enabled. When pausing background calibration leave this bit set, only change CAL_CONT to 0. If CAL_BCK is set to 0 after background calibration has been operation the calibration processes may stop in an incomplete condition. Set CAL_SFT to perform a foreground calibration

7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]

Figure 90. ADC Pattern and Over-Range Enable Register (ADC_PAT_OVR_EN)

7	6	5	4	3	2	1	0
RESERVED					ADC_PAT_EN	OR_EN	RESERVED
R/W-0000 0					R/W-0	R/W-0	R/W-0

Table 67. ADC_PAT_OVR_EN Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0000 0	Set to 00000b
2	ADC_PAT_EN	R/W	0	Enable ADC test pattern
1	OR_EN	R/W	0	Enable over-range output
0	RESERVED	R/W	0	Set to 0

7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]

Figure 91. Calibration Vectors Register (CAL_VECTOR)

7	6	5	4	3	2	1	0
CAL_DATA
R/W-0000 0000

Table 68. CAL_VECTOR Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CAL_DATA	R/W	0000 0000	Repeated reads of this register outputs all the calibration register values for analysis if the CALIBRATION_READ_WRITE_EN bit is set. Repeated writes of this register inputs all the calibration register values for configuration if the CAL_RD_EN bit is set.

7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]

Figure 92. Calibration Status Register (CAL_STAT)

7	6	5	4	3	2	1	0
RESERVED						CAL_CONT_OFF	FIRST_CAL_DONE
R-0000 10						R-X	R-X

Table 69. CAL_STAT Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0000 10XX
1	CAL_CONT_OFF	R	X	After clearing CAL_CONT, calibration does not stop immediately. Use this register to confirm it has stopped before changing calibration settings. 0: Indicates calibration is running (foreground or background) 1: Indicates that calibration is finished or stopped because CAL_CONT = 0
0	FIRST_CAL_DONE	R	X	Indicates first calibration sequence has been done and ADC is operational.

7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]

Figure 93. Timing Calibration Register (T_CAL)

7	6	5	4	3	2	1	0
RESERVED							T_AUTO
R/W-0000 001							R/W-0

Table 70. CAL_STAT Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000 001	Set to 0000001b
0	T_AUTO	R/W	0	Set to enable automatic timing optimization. Timing calibration will occur once CAL_SFT is set.

7.6.2.7 Digital Down Converter and JESD204B (0x200-0x27F)

Table 71. Digital Down Converter and JESD204B Registers

Address	Reset	Acronym	Register Name	Section
0x200	0x10	DDC_CTRL1	Digital Down-Converter (DDC) Control	Go
0x201	0x0F	JESD_CTRL1	JESD204B Control 1	Go
0x202	0x00	JESD_CTRL2	JESD204B Control 2	Go
0x203	0x00	JESD_DID	JESD204B Device ID (DID)	Go
0x204	0x00	JESD_CTRL3	JESD204B Control 3	Go
0x205	Undefined	JESD_STATUS	JESD204B and System Status Register	Go
0x206	0xF2	OVR_T0	Overrange Threshold 0	Go
0x207	0xAB	OVR_T1	Overrange Threshold 1	Go
0x208	0x00	OVR_N	Overrange Period	Go
0x209-0x20B	0x00	RESERVED	RESERVED
0x20C	0x00	NCO_MODE	DDC Configuration Preset Mode	Go
0x20D	0x00	NCO_SEL	DDC Configuration Preset Select	Go
0x20E-0x20F	0x0000	NCO_RDIV	Rational NCO Reference Divisor	Go
0x210-0x213	0xC0000000	NCO_FREQ0	NCO Frequency (Preset 0)	Go
0x214-0x215	0x0000	NCO_PHASE0	NCO Phase (Preset 0)	Go
0x216	0xFF	DDC_DLY0	DDC Delay (Preset 0)	Go
0x217	0x00	RESERVED	RESERVED
0x218-0x21B	0xC0000000	NCO_FREQ1	NCO Frequency (Preset 1)	Go
0x21C-0x21D	0x0000	NCO_PHASE1	NCO Phase (Preset 1)	Go
0x21E	0xFF	DDC_DLY1	DDC Delay (Preset 1)	Go
0x21F	0x00	RESERVED	RESERVED
0x220-0x223	0xC0000000	NCO_FREQ2	NCO Frequency (Preset 2)	Go
0x224-0x225	0x0000	NCO_PHASE2	NCO Phase (Preset 2)	Go
0x226	0xFF	DDC_DLY2	DDC Delay (Preset 2)	Go
0x227	0x00	RESERVED	RESERVED
0x228-0x22B	0xC0000000	NCO_FREQ3	NCO Frequency (Preset 3)	Go
0x22C-0x22D	0x0000	NCO_PHASE3	NCO Phase (Preset 3)	Go
0x22E	0xFF	DDC_DLY3	DDC Delay (Preset 3)	Go
0x22F	0x00	RESERVED	RESERVED
0x230-0x233	0xC0000000	NCO_FREQ4	NCO Frequency (Preset 4)	Go
0x234-0x235	0x0000	NCO_PHASE4	NCO Phase (Preset 4)	Go
0x236	0xFF	DDC_DLY4	DDC Delay (Preset 4)	Go
0x237	0x00	RESERVED	RESERVED
0x238-0x23B	0xC0000000	NCO_FREQ5	NCO Frequency (Preset 5)	Go
0x23C-0x23D	0x0000	NCO_PHASE5	NCO Phase (Preset 5)	Go
0x23E	0xFF	DDC_DLY5	DDC Delay (Preset 5)	Go
0x23F	0x00	RESERVED	RESERVED
0x240-0x243	0xC0000000	NCO_FREQ6	NCO Frequency (Preset 6)	Go
0x244-0x245	0x0000	NCO_PHASE6	NCO Phase (Preset 6)	Go
0x246	0xFF	DDC_DLY6	DDC Delay (Preset 6)	Go
0x247	0x00	RESERVED	RESERVED
0x248-0x24B	0xC0000000	NCO_FREQ7	NCO Frequency (Preset 7)	Go
0x24C-0x24D	0x0000	NCO_PHASE7	NCO Phase (Preset 7)	Go
0x24E	0xFF	DDC_DLY7	DDC Delay (Preset 7)	Go
0x24F-0x251	0x00	RESERVED	RESERVED
0x252-0x27F	Undefined	RESERVED	RESERVED

7.6.2.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]

Figure 94. Digital Down-Converter (DDC) Control Register (DDC_CTRL1)

7	6	5	4	3	2	1	0
RESERVED		SFORMAT	DDC GAIN BOOST	DMODE
R/W-00		R/W-0	R/W-1	R/W-0000

Table 72. DDC_CTRL1 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00
5	SFORMAT	R/W	0	Output sample format for bypass mode: 0 : Offset binary (default) 1 : Signed 2s complement⁽¹⁾
4	DDC GAIN BOOST	R/W	1	0 : Final filter has 0-dB gain (recommended when NCO is set near DC). 1 : Final filter has 6.02-dB gain (default)
3-0	DMODE⁽²⁾	R/W	0000	0 : Bypass mode (12-bit output, decimate-by-1, DDC off) (default) 1 : Reserved 2 : decimate-by-4 3 : decimate-by-8 4 : decimate-by-10 5 : decimate-by-16 6 : decimate-by-20 7 : decimate-by-32 8..15 : RESERVED

(1) Decimated modes always output in signed 2s complement.

(2) The DMODE setting must only be changed when JESD_EN is 0.

7.6.2.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]

Figure 95. JESD204B Control 1 Register (JESD_CTRL1)

7	6	5	4	3	2	1	0
SCR	K_Minus_1					DDR	JESD_EN
R/W-0	R/W-000 11					R/W-1	R/W-1

Table 73. JESD_CTRL1 Field Descriptions

Bit	Field	Type	Reset	Description
7	SCR	R/W	0	0 : Scrambler disabled (default) 1 : Scrambler enabled
6-2	K_Minus_1	R/W	000 11	K is the number of frames per multiframe, and K – 1 is programmed here. Default: K = 4, K_Minus_1 = 3. Depending on the decimation (D) and serial rate (DDR), there are constraints on the legal values of K.
1	DDR	R/W	1	0 : SDR serial rate (ƒ_(BIT) = ƒ_S) 1 : DDR serial rate (ƒ_(BIT) = 2ƒ_S) (default)
0	JESD_EN⁽¹⁾	R/W	1	0 : Block disabled 1 : Normal operation (default)

(1) Before altering any parameters in the JESD_CTRL1 register, you must set JESD_EN to 0. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power.

7.6.2.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00]

Figure 96. JESD204B Control 2 Register (JESD_CTRL2)

7	6	5	4	3	2	1	0
P54	SYNC_DIFFSEL	RESERVED		JESD204B_TEST
R/W-0	R/W-0	R/W-00		R/W-0000

Table 74. JESD_CTRL2 Field Descriptions

Bit	Field	Type	Reset	Description
7	P54	R/W	0	0 : Disable 5/4 PLL. Serial bit rate is 1x or 2x based on DDR parameter. 1 : Enable 5/4 PLL. Serial bit rate is 1.25x or 2.5x based on DDR parameter.
6	SYNC_DIFFSEL	R/W	0	0 : Use SYNC_SE_N input for SYNC_N function 1 : Use SYNC_DIFF_N input for SYNC_N function
5-4	RESERVED	R/W	00	Set to 00b
3-0	JESD204B_TEST⁽¹⁾	R/W	0000	See 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS15 test mode 3 : PRBS23 test mode 4 : Ramp test mode 5 : Short and long transport layer test mode 6 : D21.5 test mode 7 : K28.5 test mode 8 : Repeated ILA test mode 9 : Modified RPAT test mode 10: Serial outputs held low 11: Serial outputs held high 12 through 15 : RESERVED

(1) The JESD_CTRL2 register must only be changed when JESD_EN is 0.

7.6.2.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]

Figure 97. JESD204B Device ID (DID) Register (JESD_DID)

7	6	5	4	3	2	1	0
JESD_DID
R/W-0000 0000

Table 75. JESD_DID Field Descriptions

Bit	Field	Type	Reset	Description
7-0	JESD_DID⁽¹⁾	R/W	0000 0000	Specifies the DID value that is transmitted during the second multiframe of the JESD204B ILA.

(1) The DID setting must only be changed when JESD_EN is 0.

7.6.2.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00]

Figure 98. JESD204B Control 3 Register (JESD_CTRL3)

7	6	5	4	3	2	1	0
RESERVED						FCHAR
R/W-0000 00						R/W-00

Table 76. JESD_CTRL3 Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0000 00
1-0	FCHAR⁽¹⁾	R/W	00	Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically according to JESD204B Section 5.3.3.4. When using a JESD204B receiver, always use FCHAR=0. When using a general purpose 8-b or 10-b receiver, the K28.7 character can cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. To avoid this, program FCHAR to 1 or 2. 0 : Use K28.7 (default) (JESD204B compliant) 1 : Use K28.1 (not JESD204B compliant) 2 : Use K28.5 (not JESD204B compliant) 3 : Reserved

(1) The JESD_CTRL3 register must only be changed when JESD_EN is 0.

7.6.2.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined]

See the JESD204B Synchronization Features section for more details.

Figure 99. JESD204B and System Status Register (JESD_STATUS)

7	6	5	4	3	2	1	0
RESERVED	LINK_UP	SYNC_STATUS	REALIGNED	ALIGNED	PLL_LOCKED	RESERVED
R/W-0	R/W-0	R/W-X	R/W-X	R/W-0	R/W-0	R/W-00

Table 77. JESD_STATUS Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	Always returns 0
6	LINK_UP	R/W	0	When set, indicates that the JESD204B link is in the DATA_ENC state.
5	SYNC_STATUS	R/W	X	Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N or SYNC_DIFF_N). 0 : SYNC~ asserted 1 : SYNC~ deasserted
4	REALIGNED	R/W	X	When high, indicates that the div8 clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit clears it.
3	ALIGNED	R/W	0	When high, indicates that the multiframe clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit clears it.
2	PLL_LOCKED	R/W	0	When high, indicates that the PLL is locked.
1-0	RESERVED	R/W	0	Always returns 0

7.6.2.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]

Figure 100. Overrange Threshold 0 Register (OVR_T0)

7	6	5	4	3	2	1	0
OVR_T0
R/W-1111 0010

Table 78. OVR_T0 Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OVR_T0	R/W	1111 0010	Over-range threshold 0. This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20_log10(OVR_T0 / 256) Default: 0xF2 = 242 → –0.5 dBFS

7.6.2.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]

Figure 101. Overrange Threshold 1 Register (OVR_T1)

7	6	5	4	3	2	1	0
OVR_T1
R/W-1010 1011

Table 79. OVR_T1 Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OVR_T1	R/W	1010 1011	Overrange threshold 1. This parameter defines the absolute sample level that causes control bit 1 to be set. Control bit 1 is attached to the DDC Q output samples. The detection level in dBFS (peak) is 20_log10(OVR_T1 / 256) Default: 0xAB = 171 → –3.5 dBFS

7.6.2.7.9 Overrange Period Register (address = 0x208) [reset = 0x00]

Figure 102. Overrange Period Register (OVR_N)

7	6	5	4	3	2	1	0
RESERVED					OVR_N
R/W-0000 0					R/W-000

Table 80. OVR_N Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0000 0
2-0	OVR_N⁽¹⁾	R/W	000	This bit adjusts the monitoring period for the OVR[1:0] output bits. The period is scaled by 2^OVR_N. Incrementing this field doubles the monitoring period.

(1) Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.

7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]

Figure 103. DDC Configuration Preset Mode Register (NCO_MODE)

7	6	5	4	3	2	1	0
RESERVED							CFG_MODE
R/W-0000 000							R/W-0

Table 81. NCO_MODE Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000 000
0	CFG_MODE	R/W	0	The NCO frequency and phase are set by the NCO_FREQx and NCO_PHASEx registers, where x is the configuration preset (0 through 7). The DDC delay setting is defined by the DDC_DLYx register. 0 : Use NCO_[2:0] input pins to select the active DDC and NCO configuration preset. 1 : Use the NCO_SEL register to select the active DDC and NCO configuration preset.

7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]

Figure 104. DDC Configuration Preset Select Register (NCO_SEL)

7	6	5	4	3	2	1	0
RESERVED					NCO_SEL
R/W-0000 0					R/W-000

Table 82. NCO_SEL Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0000 0
2-0	NCO_SEL	R/W	000	When NCO_MODE = 1, this register is used to select the active configuration preset.

7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]

Figure 105. Rational NCO Reference Divisor Register (NCO_RDIV)

15	14	13	12	11	10	9	8
NCO_RDIV
R/W-0x00h

7	6	5	4	3	2	1	0
NCO_RDIV
R/W-0x00h

Table 83. NCO_RDIV Field Descriptions

Bit	Field	Type	Reset	Description
15-0	NCO_RDIV	R/W	0x0000h	Sometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This results in a frequency error. Use this register to eliminate the frequency error. Use this equation to compute the proper value to program: Equation 10. NCO_RDIV = ƒ_S / ƒ_(STEP) / 128 where ƒ_S is the ADC sample rate ƒ_(STEP) is the desired NCO frequency step size For example, if ƒ_S= 3072 MHz, and ƒ_(STEP)= 10 KHz then: Equation 11. NCO_RDIV = 3072 MHz / 10 KHz / 128 = 2400 Any combination of ƒ_S and ƒ_(STEP) that results in a fractional value for NCO_RDIV is not supported. Values of NCO_RDIV larger than 8192 can degrade the NCO’s SFDR performance and are not recommended. This register is used for all configuration presets.

7.6.2.7.13 NCO Frequency (Preset x) Register (address = see Table 71) [reset = see Table 71]

Figure 106. NCO Frequency (Preset x) Register (NCO_FREQ_x)

31	30	29	28	27	26	25	24
NCO_FREQ_x
R/W-0xC0h

23	22	21	20	19	18	17	16
NCO_FREQ_x
R/W-0x00h

15	14	13	12	11	10	9	8
NCO_FREQ_x
R/W-0x00h

7	6	5	4	3	2	1	0
NCO_FREQ_x
R/W-0x00h

Table 84. NCO_FREQ_x Field Descriptions

Bit	Field	Type	Reset	Description
31-0	NCO_FREQ_x	R/W	0xC0000000h	Changing this register after the JESD204B interface is running results in non-deterministic NCO phase. If deterministic phase is required, the JESD204B interface must be re-initialized after changing this register. The NCO frequency (ƒ_(NCO)) is: Equation 12. ƒ_(NCO) = NCO_FREQ_x × 2^–32 × ƒ_S where ƒ_S is the sampling frequency of the ADC NCO_FREQ_x is the integer value of this register This register can be interpreted as signed or unsigned. Use this equation to determine the value to program: Equation 13. NCO_FREQ_x = 2³² × ƒ_(NCO) / ƒ_S If the equation does not result in an integer value, you must choose an alternate frequency step (ƒ_(STEP)) and program the NCO_RDIV register. Then use one of the following equations to compute NCO_FREQ_x: Equation 14. NCO_FREQ_x = round(2³² × ƒ_(NCO) / ƒ_S) Equation 15. NCO_FREQ_x = round(2²⁵ × ƒ_(NCO) / ƒ_(STEP) / NCO_RDIV)

7.6.2.7.14 NCO Phase (Preset x) Register (address = see Table 71) [reset = see Table 71]

Figure 107. NCO Phase (Preset) Register (NCO_PHASE_x)

15	14	13	12	11	10	9	8
NCO_PHASE_x
R/W-0x00h

7	6	5	4	3	2	1	0
NCO_PHASE_x
R/W-0x00h

Table 85. NCO_PHASE_x Field Descriptions

Bit	Field	Type	Reset	Description
15-0	NCO_PHASE_x	R/W	0x0000h	This value is MSB-justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is Equation 16. NCO_PHASE_x × 2^–16 × 2π This register can be interpreted as signed or unsigned.

7.6.2.7.15 DDC Delay (Preset x) Register (address = see Table 71) [reset = see Table 71]

Figure 108. DDC Delay (Preset) Register (DDC_DLY_x)

7	6	5	4	3	2	1	0
DDC_DLY_x
R/W-0xFFh

Table 86. DDC_DLY_x Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DDC_DLY_x	R/W	0xFFh	DDC delay for configuration preset 0 This register provides fine adjustments to the DDC group delay. The step size is one half of an ADC sample period (t_(DEVCLK) / 2). This is equivalent to Equation 17. Equation 17. t_O / (2 × D) where t_O is the DDC output sample period D is the decimation factor The legal range for this register is 0 to 2D-1. Illegal values result in undefined behavior. Example: When D = 8, the legal register range is 0 to 15. The step size is t_O / 16 and the maximum delay is 15 × t_O / 16. Programming this register to 0xFF (the default value) powers down and bypasses the fractional delay filter which reduces the DDC latency by 34 ADC sample periods (as compared to the 0 setting).

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7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Signal Acquisition

7.3.2 The Analog Inputs

7.3.2.1 Input Clamp

7.3.2.2 AC Coupled Input Usage

Table 1. Balun Recommendations

7.3.2.3 DC Coupled Input Usage

Table 2. Amplifier Recommendations

7.3.2.4 Handling Single-Ended Input Signals

7.3.3 Clocking

7.3.4 Over-Range Function

Table 3. Threshold and Monitor Period for Embedded OR Bits

Table 4. Over-Range Monitoring Period

7.3.5 ADC Core Features

7.3.5.1 The Reference Voltage

7.3.5.2 Common-Mode Voltage Generation

7.3.5.3 Bias Current Generation

7.3.5.4 Full Scale Range Adjust

7.3.5.5 Offset Adjust

7.3.5.6 Power-Down

7.3.5.7 Built-In Temperature Monitor Diode

7.3.6 Digital Down Converter (DDC)

7.3.6.1 NCO/Mixer

7.3.6.2 NCO Settings

7.3.6.2.1 NCO Frequency Phase Selection

7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)

7.3.6.2.3 NCO_SEL Bits (2:0)

7.3.6.2.4 NCO Frequency Setting (Eight Total)

7.3.6.2.4.1 Basic NCO Frequency-Setting Mode

7.3.6.2.4.2 Rational NCO Frequency Setting Mode

Table 5. Common NCO_RDIV Values (For 10-kHz Frequency Steps)

7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)

7.3.6.2.6 Programmable DDC Delay

Table 6. Programmable DDC Delay Range

7.3.6.3 Decimation Filters

Table 7. Output Sample Rates

Table 8. Decimation Mode Filter Usage

Table 9. Filter Coefficient Details

7.3.6.4 DDC Output Data

7.3.6.5 Decimation Settings

7.3.6.5.1 Decimation Factor

7.3.6.5.2 DDC Gain Boost

7.3.7 Data Outputs

7.3.7.1 The Digital Outputs

7.3.7.2 JESD204B Interface Features and Settings

7.3.7.2.1 Scrambler Enable

7.3.7.2.2 Frames Per Multi-Frame (K-1)

7.3.7.2.3 DDR

7.3.7.2.4 JESD Enable

7.3.7.2.5 JESD Test Modes

7.3.7.2.6 Configurable Pre-Emphasis

7.3.7.2.7 Serial Output-Data Formatting

Table 10. Parameter Definitions

Table 11. Serial Link Parameters(1)

Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8

Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters

Table 14. Decimate-by-4, DDR = 1, P54 = 0, LMF = 5,2,4

Table 15. Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2

Table 16. Decimate-by-8, DDR = 0, P54 = 0, LMF = 5,2,4

Table 17. Decimate-by-8, DDR = 0, P54 = 1, LMF = 4,2,2

Table 18. Decimate-by-8, DDR = 1, P54 = 0, LMF = 3,2,8

Table 19. Decimate-by-8, DDR = 1, P54=1, LMF = 2,2,2

Table 20. Decimate-by-10, DDR = 0, P54 = 0, LMF = 4,2,2

Table 21. Decimate-by-10, DDR = 1, P54 = 0, LMF = 2,2,2

Table 22. Decimate-by-16, DDR = 0, P54 = 0, LMF = 3,2,8

Table 23. Decimate-by-16, DDR = 0, P54 = 1, LMF = 2,2,2

Table 24. Decimate-by-16, DDR = 1, P54 = 0, LMF = 2,2,16

Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4

Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2

Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2

Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16

Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4

Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32

Table 11. Serial Link Parameters⁽¹⁾

Table 33. ADC Test Pattern⁽¹⁾