JAJSNR5A june   2022  – july 2023 ADC12QJ1600-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Switching Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Protection
        2. 8.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.1.3 Analog Input Offset Adjust
        4. 8.3.1.4 ADC Core
          1. 8.3.1.4.1 ADC Theory of Operation
          2. 8.3.1.4.2 ADC Core Calibration
          3. 8.3.1.4.3 Analog Reference Voltage
          4. 8.3.1.4.4 ADC Over-range Detection
          5. 8.3.1.4.5 Code Error Rate (CER)
      2. 8.3.2 Temperature Monitoring Diode
      3. 8.3.3 Timestamp
      4. 8.3.4 Clocking
        1. 8.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 8.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 8.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 8.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 8.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 8.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 8.3.5 JESD204C Interface
        1. 8.3.5.1  Transport Layer
        2. 8.3.5.2  Scrambler
        3. 8.3.5.3  Link Layer
        4. 8.3.5.4  8B or 10B Link Layer
          1. 8.3.5.4.1 Data Encoding (8B or 10B)
          2. 8.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.5.4.3 Code Group Synchronization (CGS)
          4. 8.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.5.4.5 Frame and Multiframe Monitoring
        5. 8.3.5.5  64B or 66B Link Layer
          1. 8.3.5.5.1 64B or 66B Encoding
          2. 8.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 8.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 8.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 8.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 8.3.5.5.3 Initial Lane Alignment
          4. 8.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.5.6  Physical Layer
          1. 8.3.5.6.1 SerDes Pre-Emphasis
        7. 8.3.5.7  JESD204C Enable
        8. 8.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 8.3.5.9  Operation in Subclass 0 Systems
        10. 8.3.5.10 Alarm Monitoring
          1. 8.3.5.10.1 Clock Upset Detection
          2. 8.3.5.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1 Serializer Test-Mode Details
        2. 8.4.4.2 PRBS Test Modes
        3. 8.4.4.3 Clock Pattern Mode
        4. 8.4.4.4 Ramp Test Mode
        5. 8.4.4.5 Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6 D21.5 Test Mode
        7. 8.4.4.7 K28.5 Test Mode
        8. 8.4.4.8 Repeated ILA Test Mode
        9. 8.4.4.9 Modified RPAT Test Mode
      5. 8.4.5 Calibration Modes and Trimming
        1. 8.4.5.1 Foreground Calibration Mode
        2. 8.4.5.2 Background Calibration Mode
        3. 8.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 8.4.6 Offset Calibration
      7. 8.4.7 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
      7. 8.5.7 SPI_Register_Map Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Sequencing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ALR|144
サーマルパッド・メカニカル・データ
発注情報

7.8 Switching Characteristics

typical values at TJ = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 97 MHz, AIN = –1 dBFS, fCLK = 1.6 GHz, filtered 1-VPP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration, SER_PE = 4 (unless otherwise noted); VA11Q and VCLK11 noise suppression on when CPLL on; minimum and maximum values are at nominal supply voltages and over the operating junction temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC SAMPLING CLOCK
tAD Sampling (aperture) delay from the clock falling edge to sampling instant PLL disabled, CLK± 305 ps
PLL enabled, CLK± 314 ps
PLL enabled, SE_CLK 332 ps
tAJ Aperture jitter, rms Dither disabled (ADC_DITH_EN = 0) 50 fs
Dither enabled (ADC_DITH_EN = 1) 60 fs
tJ(PLL) PLL additive jitter, rms PLL enabled (PLL_EN = 1), fPLLREF = 50 MHz 358 fs
tJ(PLL) PLL additive jitter, rms PLL enabled (PLL_EN = 1), fPLLREF = 200 MHz 340 fs
CLOCK AND TRIGGER OUTPUTS (PLLREFO±, TRIGOUT±, ORC, ORD)
fPLLREFO PLLREFO± frequency range PLL Enabled, PLLREFO± enabled 50 500 MHz
fDIVREFO ORC and ORD frequency range when programmed to output divided PLL reference clock PLL Enabled, DIVREF_C_MODE > 0, DIVREF_D_MODE > 0 12.5 100 MHz
tPW(TRIGOUT) Minimum TRIGOUT± pulse width TRIGOUT_SRC = 0 (TMSTP±) 1 tCLK
fTRIGOUT TRIGOUT± frequency range TRIGOUT_SRC = 1 (S-PLL) 800 MHz
tPD(REF) Input clock to PLLREFO± propagation delay PLLREF_SE = 0 (CLK± used), nominal supply voltage, TA = 25°C 280 359 440 ps
PLLREF_SE = 1 (SE_CLK used), nominal supply voltage, TA = 25°C 380 469 560
tPD-TEMPCO Input clock to PLLREFO± propagation delay temperature coefficient PLLREF_SE = 0 (CLK± used), nominal supply voltage 250 330 420 fs/°C
PLLREF_SE = 1 (SE_CLK used), nominal supply voltage 280 365 450
tPD-VOLTCO Input clock to PLLREFO± propagation delay supply voltage coefficient PLLREF_SE = 0 (CLK± used), TA = 25°C –533 –397 –186 fs/mV
PLLREF_SE = 1 (SE_CLK used), TA = 25°C –480 –372 –180
SERIAL DATA OUTPUTS (D[7:0]+, D[7:0]–)
fSERDES Serialized output bit rate 2.5 17.16 Gbps
UI Serialized output unit interval 58.3 400 ps
tTLH Low-to-high transition time (differential) 20% to 80%, 8H8L test pattern, 16.5 Gbps 28 ps
tTHL High-to-low transition time (differential) 20% to 80%, 8H8L test pattern, 16.5 Gbps 28 ps
DDJ Data dependent jitter, peak-to-peak PRBS-7 test pattern, JMODE = 0, 12.8 Gbps 8.56 ps
PRBS-9 test pattern, JMODE = 4, 16.5 Gbps 6.9
PRBS-9 test pattern, JMODE = 8, 17.16 Gbps 9.28
DCD Even-odd jitter, peak-to-peak PRBS-7 test pattern, JMODE = 0, 12.8 Gbps 0.2 ps
PRBS-9 test pattern, JMODE = 4, 16.5 Gbps 0.01
PRBS-9 test pattern, JMODE = 8, 17.16 Gbps 0.05
EBUJ Effective bounded uncorrelated jitter, peak-to-peak PRBS-7 test pattern, JMODE = 0, 12.8 Gbps 1.63 ps
PRBS-9 test pattern, JMODE = 4, 16.5 Gbps 0.85
PRBS-9 test pattern, JMODE = 8, 17.16 Gbps 3.12
RJ Unbounded random jitter, RMS 8H8L test pattern, JMODE = 0, 12.8 Gbps 0.88 ps
8H8L test pattern, JMODE = 4, 16.5 Gbps 0.72
8H8L test pattern, JMODE = 8, 17.16 Gbps 1
TJ Total jitter, peak-to-peak, with unbounded random jitter portion defined with respect to a BER = 1e-15 (Q = 7.94) PRBS-7 test pattern, JMODE = 0, 12.8 Gbps 21.35 ps
PRBS-9 test pattern, JMODE = 4, 16.5 Gbps 18.01
PRBS-9 test pattern, JMODE = 8, 17.16 Gbps 23.78
ADC CORE LATENCY
tADC Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high(1) JMODE = 0 –2 tCLK cycles
JMODE = 1 1
JMODE = 2 –1
JMODE = 3 –1
JMODE = 4 –1
JMODE = 5 –1
JMODE = 6 1
JMODE = 7 –1
JMODE = 8 –1
JMODE = 9 –1
JMODE = 10 –2
JMODE = 11 –2
JMODE = 12 –1
JMODE = 13 2
JMODE = 14 –2
JMODE = 15 –2
JESD204C AND SERIALIZER LATENCY
tTX Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe (8B/10B encoding) or extended multiblock (64B/66B encoding) on the JESD204C serial output lane corresponding to the reference sample of tADC(2) JMODE = 0 49.8 56.6 tCLK cycles
JMODE = 1 45.5 52.8
JMODE = 2 45.5 52.8
JMODE = 3 44.3 50.5
JMODE = 4 42.1 48
JMODE = 5 42.1 48
JMODE = 6 53.3 60.2
JMODE = 7 53.3 60.2
JMODE = 8 47.1 54.2
JMODE = 9 58.4 65
JMODE = 10 56.2 63.1
JMODE = 11 66.3 74.5
JMODE = 12 87.2 94.8
JMODE = 13 72.9 83.9
JMODE = 14 61.7 68.1
JMODE = 15 94 103.3
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD) Delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from tri-state to valid data 1 ns
t(ODZ) Delay from the SCS rising edge for SDO transition from valid data to tri-state 10 ns
t(OD) Delay from the falling edge of SCLK during read operation to SDO valid 1 10 ns
(1) tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by tTX.
(2) The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.