JAJSMI3
October 2021
ADC12DJ1600
,
ADC12QJ1600
,
ADC12SJ1600
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
概要 (続き)
5
Revision History
6
Device Comparison
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics: DC Specifications
8.6
Electrical Characteristics: Power Consumption
8.7
Electrical Characteristics: AC Specifications
8.8
Timing Requirements
8.9
Switching Characteristics
8.10
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Analog Input
9.3.1.1
Analog Input Protection
9.3.1.2
Full-Scale Voltage (VFS) Adjustment
9.3.1.3
Analog Input Offset Adjust
9.3.1.4
ADC Core
9.3.1.4.1
ADC Theory of Operation
9.3.1.4.2
ADC Core Calibration
9.3.1.4.3
Analog Reference Voltage
9.3.1.4.4
ADC Over-range Detection
9.3.1.4.5
Code Error Rate (CER)
9.3.2
Temperature Monitoring Diode
9.3.3
Timestamp
9.3.4
Clocking
9.3.4.1
Converter PLL (C-PLL) for Sampling Clock Generation
9.3.4.2
LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
9.3.4.3
Optional CMOS Clock Outputs (ORC, ORD)
9.3.4.4
SYSREF for JESD204C Subclass-1 Deterministic Latency
9.3.4.4.1
SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
9.3.4.4.2
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
9.3.5
JESD204C Interface
9.3.5.1
Transport Layer
9.3.5.2
Scrambler
9.3.5.3
Link Layer
9.3.5.4
8B or 10B Link Layer
9.3.5.4.1
Data Encoding (8B or 10B)
9.3.5.4.2
Multiiframes and the Local Multiframe Clock (LMFC)
9.3.5.4.3
Code Group Synchronization (CGS)
9.3.5.4.4
Initial Lane Alignment Sequence (ILAS)
9.3.5.4.5
Frame and Multiframe Monitoring
9.3.5.5
64B or 66B Link Layer
9.3.5.5.1
64B or 66B Encoding
9.3.5.5.2
Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
9.3.5.5.2.1
Block, Multiblock and Extended Multiblock Alignment using Sync Header
9.3.5.5.2.1.1
Cyclic Redundancy Check (CRC) Mode
9.3.5.5.2.1.2
Forward Error Correction (FEC) Mode
9.3.5.5.3
Initial Lane Alignment
9.3.5.5.4
Block, Multiblock and Extended Multiblock Alignment Monitoring
9.3.5.6
Physical Layer
9.3.5.6.1
SerDes Pre-Emphasis
9.3.5.7
JESD204C Enable
9.3.5.8
Multi-Device Synchronization and Deterministic Latency
9.3.5.9
Operation in Subclass 0 Systems
9.3.5.10
Alarm Monitoring
9.3.5.10.1
Clock Upset Detection
9.3.5.10.2
FIFO Upset Detection
9.4
Device Functional Modes
9.4.1
Low Power Mode and High Performance Mode
9.4.2
JESD204C Modes
9.4.2.1
JESD204C Transport Layer Data Formats
9.4.2.2
64B or 66B Sync Header Stream Configuration
9.4.2.3
Redundant Data Mode (Alternate Lanes)
9.4.3
Power-Down Modes
9.4.4
Test Modes
9.4.4.1
Serializer Test-Mode Details
9.4.4.2
PRBS Test Modes
9.4.4.3
Clock Pattern Mode
9.4.4.4
Ramp Test Mode
9.4.4.5
Short and Long Transport Test Mode
9.4.4.5.1
Short Transport Test Pattern
9.4.4.6
D21.5 Test Mode
9.4.4.7
K28.5 Test Mode
9.4.4.8
Repeated ILA Test Mode
9.4.4.9
Modified RPAT Test Mode
9.4.5
Calibration Modes and Trimming
9.4.5.1
Foreground Calibration Mode
9.4.5.2
Background Calibration Mode
9.4.5.3
Low-Power Background Calibration (LPBG) Mode
9.4.6
Offset Calibration
9.4.7
Trimming
9.5
Programming
9.5.1
Using the Serial Interface
9.5.2
SCS
9.5.3
SCLK
9.5.4
SDI
9.5.5
SDO
9.5.6
Streaming Mode
9.5.7
SPI_Register_Map Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Light Detection and Ranging (LiDAR) Digitizer
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
Analog Front-End Requirements
10.2.1.2.2
Calculating Clock and SerDes Frequencies
10.2.1.3
Application Curves
10.3
Initialization Set Up
11
Power Supply Recommendations
11.1
Power Sequencing
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.2
Receiving Notification of Documentation Updates
13.3
サポート・リソース
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
AAV|144
MPBGAM2C
サーマルパッド・メカニカル・データ
発注情報
jajsmi3_oa
9
Detailed Description