JAJSMN4A July 2021 – October 2024 ADC12DJ800-Q1 , ADC12QJ800-Q1 , ADC12SJ800-Q1
PRODUCTION DATA
The device can operate with subclass 0 compatibility provided that multi-ADC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as normal to initiate the CGS and ILAS in 8B/10B mode.