The ADC12xJ800-Q1 is a family of quad, dual and single channel 12-bit, 800MSPS analog-to-digital converters (ADC). The devices have been optimized for low power consumption while maintaining high sampling rate and performance. The combination of power consumption, sampling rate and 12-bit resolution makes the device is ideally suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is AEC-Q100 grade 1 (-40°C to 125°C) qualified for automotive applications.

The device has a buffered input with full-power input bandwidth (-3dB) of 6GHz. The wide input bandwidth provides flat frequency response for frequency domain applications, such as frequency modulated continuous wave (FMCW) LiDAR systems, and provides a narrow impulse response for time domain applications, such as and pulse-based LiDAR to achieve increased spatial resolution.

A number of clocking features are included to relax system timing requirements and simplify system architectures. The device has an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock from a low frequency reference eliminating the need for an external high frequency clock generator. The low frequency PLL reference also relaxes timing of the SYSREF timing reference to achieve deterministic latency and multi-device synchronization. The internal PLL can be bypassed in favor of sending the high frequency sampling clock directly to the device for highest performance. A SYSREF Windowing feature relaxes the setup and hold requirement of SYSREF by directly measuring and adjusting the SYSREF delay inside of the device without the need to meet external timing requirements. The PLL reference clock can be output from the device to clock the digital logic FPGA or ASIC or an adjacent device to eliminate external clock buffer and distribution devices. Two additional CMOS outputs can send copies or divided copies of the PLL reference clock to clock additional devices in the system. A fourth clock output can output a SerDes reference clock for the transceiver block in the FPGA or ASIC to provide a complete system clocking solution. A timestamp input can be used to mark a specific sample using an external trigger. The timestamp is output over the JESD204C interface to mark the sample in the FPGA or ASIC. The timestamp signal can optionally be output from the device instead of the SerDes reference clock to replicate the retimed trigger to other devices, such as the pulse driver for a laser diode.

The JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing by increasing the SerDes bitrate per lane and therefore decreasing the number of lanes required. JESD204C interface modes support from one to four lanes (single channel device) or two to eight lanes (dual and quad channel devices) and SerDes baud-rates up to 17.16Gbps to allow each application to choose the optimal configuration. Both 8B/10B and 64B/66B data encoding options are available. The 8B/10B encoding modes are backwards compatible with JESD204B receivers while the 64B/66B encoding modes provide higher efficiency by reducing link overhead.