SNOI146C September   2011  – December 2017 ADC141S628-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 ADC141S628-Q1 Converter Electrical Characteristics
    5. 6.5 ADC141S628-Q1 Timing Requirements
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Reference Input (VREF)
      2. 7.2.2 Analog Signal Inputs
      3. 7.2.3 Pseudo-Differential Operation
      4. 7.2.4 Serial Digital Interface
      5. 7.2.5 CS Input
      6. 7.2.6 SCLK Input
      7. 7.2.7 Data Output
    3. 7.3 Device Functional Modes
      1. 7.3.1 Power Consumption
        1. 7.3.1.1 Short Cycling
        2. 7.3.1.2 Burst Mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Circuits
        1. 8.1.1.1 Data Acquisition
  9. 9 Power Supply Recommendations
    1. 9.1 Analog and Digital Power Supplies
    2. 9.2 Voltage Reference
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Specification Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

9 Power Supply Recommendations

9.1 Analog and Digital Power Supplies

Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC141S628-Q1 must be clean and well bypassed. Use a 0.1-µF ceramic bypass capacitor and a 1-µF to 10-µF capacitor to bypass the ADC141S628-Q1 supply, with the 0.1-µF capacitor placed as close to the ADC141S628-Q1 package as possible.

Because the ADC141S628-Q1 has both the VA and VIO pins, the user has three options on how to connect these pins. The first option is to tie VA and VIO together and power them with the same power supply. This connection is the most cost effective way of powering the ADC141S628-Q1 but is also the least ideal. As stated previously, noise from VIO can couple into VA and adversely affect performance. The other two options involve the user powering VA and VIO with separate supply voltages. These supply voltages can have the same amplitude or they can be different. These voltages may be set independent of each other and can be any value between 4.5 V and 5.5 V.

Best performance is typically achieved with VA operating at 5 V. Operating VA at 5 V offers the best linearity and dynamic performance when VREF is also set to 5 V.

9.2 Voltage Reference

The reference source must have a low output impedance and must be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1-µF capacitor is preferred. While the ADC141S628-Q1 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference.

The VREF of the ADC141S628-Q1, like all ADCs, does not reject noise or voltage variations. Keep this fact in mind if VREF is derived from the power supply. Any noise or ripple from the supply that is not rejected by the external reference circuitry appears in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are excellent choices for a reference source.