SLASE49B December   2015  – April 2017 ADC14X250

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Static Converter Performance
    6. 6.6  Electrical Characteristics: Dynamic Converter Performance
    7. 6.7  Electrical Characteristics: Power Supply
    8. 6.8  Electrical Characteristics: Analog Interface
    9. 6.9  Digital Input Characteristics
    10. 6.10 Electrical Characteristics: Serial Data Output Interface
    11. 6.11 Electrical Characteristics: Digital Input
    12. 6.12 Timing Requirements
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 JESD204B Interface Functional Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  Input Clock Divider
      3. 8.3.3  SYSREF Offset Feature and Detection Gate
      4. 8.3.4  DC Offset Correction
      5. 8.3.5  Serial Differential Output Drivers
        1. 8.3.5.1 De-Emphasis Equalization
      6. 8.3.6  ADC Core Calibration
      7. 8.3.7  Data Format
      8. 8.3.8  JESD204B Supported Features
      9. 8.3.9  Transport Layer Configuration
        1. 8.3.9.1 Lane Configuration
        2. 8.3.9.2 Frame Format
        3. 8.3.9.3 ILA Information
      10. 8.3.10 Test Pattern Sequences
      11. 8.3.11 JESD204B Link Initialization
        1. 8.3.11.1 Frame Alignment
        2. 8.3.11.2 Code Group Synchronization
      12. 8.3.12 Sync~ Signal Selection
      13. 8.3.13 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
        1. 8.5.1.1  CONFIG_A, [Address: 0x0000], [Default: 0x3C]
        2. 8.5.1.2  DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]
        3. 8.5.1.3  CHIP_TYPE, [Address: 0x0003], [Default: 0x03]
        4. 8.5.1.4  CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]
        5. 8.5.1.5  CHIP_VERSION, [Address: 0x0006], [Default: 0x00]
        6. 8.5.1.6  VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]
        7. 8.5.1.7  SPI_CFG, [Address: 0x0010], [Default: 0x01]
        8. 8.5.1.8  OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]
        9. 8.5.1.9  OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]
        10. 8.5.1.10 IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]
        11. 8.5.1.11 DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]
        12. 8.5.1.12 SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]
        13. 8.5.1.13 JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]
        14. 8.5.1.14 JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]
        15. 8.5.1.15 JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]
        16. 8.5.1.16 JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Clock Configuration Examples
        4. 9.1.4.4 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Design Procedure
      3. 9.2.3 Application Performance Plot
      4. 9.2.4 Systems Example
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Specification Definitions
        2. 12.1.1.2 JESD204B Definitions
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

The ADC14X250 device is a single channel analog-to-digital converter (ADC) composed of pipelined stages and followed by a back-end JESD204B interface. The ADC core is preceded by an input buffer and imbalance correction circuit at the analog input and is provided with the necessary reference voltages with internal drivers that require no external components. The analog input common-mode is also internally regulated.

A DC offset correction block is disabled by default, but may also be enabled at the ADC core output to remove DC offset. Processed data is passed into the JESD204B interface where the data is framed, encoded, serialized, and output on one lane per channel. Data is serially transmitted by configurable high-speed voltage mode drivers.

The sampling clock is derived from the CLKIN input via a low-noise receiver and clock divider. The CLKIN, SYSREF, and SYNCb inputs provide the device clock, sysref, and sync~ signals to the JESD204B interface, which are used to derive the internal local frame and local multi-frame clocks and establish the serial link.

Features of the ADC14X250 device are configurable through the 4-wire SPI.

Functional Block Diagram

ADC14X250 ADC14X250_Block_Diagram.gif

Feature Description

Amplitude and Phase Imbalance Correction of Differential Analog Input

The ADC performance can be sensitive to amplitude and phase imbalance of the input differential signal and therefore integrates a front-end balance correction circuit to optimize the second-order distortion (HD2) performance of the ADC in the presence of an imbalanced input signal. 4-bit control of the phase mismatch and 3-bit control of the amplitude mismatch corrects the input mismatch before the input buffer. A simplified diagram of the amplitude and phase correction circuit at the ADC input is shown in Figure 32.

ADC14X250 ImbCorr_Circuit.gif Figure 32. Simplified Input Differential Balance Correction Circuit

Amplitude correction is achieved by varying the single-ended termination resistance of each input while maintaining constant total differential resistance, thereby adjusting the amplitude at each input but leaving the differential swing constant. Phase correction, also considered capacitive balance correction, varies the capacitive load at the ADC input, thereby correcting a phase imbalance by creating a bandwidth difference between the analog inputs that minimally affects amplitude. This function is useful for correcting the balance of transformers or filters that drive the ADC analog inputs. Figure 33 shows the measured HD2 resulting from an example 240-MHz imbalanced signal input into the ADC14X250 device recorded over the available amplitude and phase correction settings, demonstrating the optimization of HD2. Performance parameters in the Electrical Characteristics: Dynamic Converter Performance are characterized with the amplitude and phase correction settings in the default condition.

ADC14X250 ADC14X250_imbalance_correction.jpg Figure 33. Gain and Phase Imbalance HD2 Optimization

Input Clock Divider

An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally divided down at the ADC device so that coupling of signals at common intermediate frequencies into other parts of the system can be avoided. The frequency at the CLKIN input may be divided down to the sampling rate of the ADC by factors of 1, 2, 4, or 8. Changing the clock divider setting initiates a JESD204 link re-initialization and requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration.

SYSREF Offset Feature and Detection Gate

When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be in an idle state. The idle state is recommended at any time the ADC14X250 spurious performance must be maximized. When the SYSREF signal is in the idle state for longer than 1 µs, an undesirable offset voltage may build up across the AC coupling capacitors between the SYSREF transmitter and the ADC14X250 device input. This offset voltage creates a signal threshold problem, requires a long time to dissipate, and therefore prevents quick transition of the SYSREF signal out of the idle state. Two features are provided as a solution and are shown in Figure 50, namely the SYSREF offset feature and SYSREF detection gate.

In the case that the SYSREF signal idle state has a 0-V differential value, or if the ADC14X250 device must be insensitive to noise that may appear on the SYSREF signal, then the SYSREF detection gate may be used. The detection gate is the AND gate shown in Figure 50 that enables or disables propagation of the SYSREF signal through to the internal device logic. If the detection gate is disabled and a false edge appears at the SYSREF input, the signal does not disrupt the internal clock alignment. Note that the SYSREF detection gate is disabled by default; therefore, the device does not respond to a SYSREF edge until the detection gate is enabled.

The SYSREF offset and detection gate features are both controlled through the SPI.

DC Offset Correction

DC offset correction is provided using a digital high-pass IIR filter at the immediate output of the ADC core. The DC offset correction is bypassed by default, but may be enabled and configured via the SPI. The 3-dB bandwidth of the IIR digital correction filter may be set to four different low-frequency values. When DC offset correction is enabled, any signal in the stop-band of the high-pass filter is attenuated. The settling time of the DC offset correction is approximately equal to the inverse of the 3-dB bandwidth setting.

Serial Differential Output Drivers

The differential drivers of the ADC14X250 device that output the serial JESD204B data are voltage mode drivers with amplitude control and de-emphasis features that may be configured through the SPI for a variety of different channel applications. Eight amplitude control (VOD) and eight de-emphasis control (DEM) settings are available. Both VOD and DEM register fields must be configured to optimize the noise performance of the serial interface for a particular lossy channel.

The output common-mode of the driver varies with the configuration of the output swing. Therefore, AC coupling is strongly recommended between the ADC14X250 device and the device receiving the serial data.

De-Emphasis Equalization

De-emphasis of the differential output is provided as a form of continuous-time linear equalization that imposes a high-pass frequency response onto the output signal to compensate for frequency-dependent attenuation as the signal propagates through the channel to the receiver. In the time-domain, the de-emphasis appears as the bit transition transient followed by an immediate reduction in the differential amplitude, as shown in Figure 34. The characteristic appearance of the waveform changes with differential amplitude and the magnitude of de-emphasis applied. The serial lane rate determines the available period of time during which the de-emphasis transient settles. However, the lane rate does not affect the settling behavior of the applied de-emphasis.

ADC14X250 Deemphasis_waveform.png Figure 34. De-emphasis of the Differential Output Signal

Table 1 indicates the typical measured values for the de-emphasis range, where the de-emphasis value is measured as the ratio (in units of [dB]) between the peak voltage after the signal transition to the settled voltage value in one bit period. The data rate for this measurement is 1.2 Gb/s to allow settling of the de-emphasis transient. Table 1 illustrates the actual de-emphasis value in terms of voltage attenuation and shows dependence on the amplitude setting, but does not reflect the optimal amplitude setting (VOD) and de-emphasis setting (DEM) for a particular lossy channel. Table 2 shows the amplitude of the differential signal swing during its settled state after the transition transient. The measurement is performed at 1.2 Gb/s and the units are in differential peak-to-peak mV.

Table 1. De-Emphasis Values (dB) for All VOD and DEM Configuration Settings

DEM
0 1 2 3 4 5 6 7
VOD 0 0 –0.2 –1.1 –2.2 –3.0 –4.3 –5.6 –8.5
1 0 –0.4 –1.7 –2.9 –3.8 –5.1 –6.5 –9.6
2 0 –0.7 –2.2 –3.5 –4.5 –5.9 –7.4 –10.4
3 0 –1.0 –2.8 –4.2 –5.2 –6.7 –8.1 –11.2
4 0 –1.4 –3.4 –4.9 –5.9 –7.4 –8.9 –12.1
5 0 –1.7 –3.9 –5.5 –6.5 –8.0 –9.5 –12.7
6 0 –2.1 –4.4 –6.0 –7.1 –8.6 –10.2 –13.4
7 0 –2.5 –4.9 –6.5 –7.6 –9.2 –10.7 –14.0

Table 2. Settled Differential Voltage Swing Values, VOD (mV-peak-peak) for All VOD and DEM Configuration Settings

DEM
0 1 2 3 4 5 6 7
VOD 0 570 550 500 440 400 350 300 210
1 660 630 550 470 430 370 310 220
2 750 690 580 500 450 380 320 230
3 840 750 610 520 460 390 330 230
4 940 800 630 530 470 400 340 230
5 1020 840 650 550 480 410 340 240
6 1110 870 670 560 490 410 340 240
7 1200 900 680 570 500 420 350 240

ADC Core Calibration

After power-up, the ADC14X250 device detects that the supplies and clock are valid, waits for a power-up delay, and then performs a calibration of the ADC core automatically. The power-up delay is 8.4 × 106 sampling clock cycles or 33.6 ms at a 250-MSPS sampling rate. The calibration requires approximately 1.0 × 106 sampling clock cycles.

If the system requires that the ADC14X250 input clock divider value (CLKDIV) is set to 2, 4, or 8, then ADC calibration must be performed manually after CLKDIV has been set to the desired value. Manual calibration is performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the system may wait 1.5 × 106 sampling clock cycles until calibration is complete.

Re-calibration is not required across the supported operating temperature range to maintain functional performance, but it is recommended for large changes in ambient temperature to maintain optimal dynamic performance. Changing the sampling rate always requires re-calibration of the ADC core. For more information about device modes, see Power-Down and Sleep Modes.

Data Format

Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing, scrambling and 8b/10b encoding.

JESD204B Supported Features

The ADC14X250 device supports a feature set of the JESD204B standard targeted to its intended applications but does not implement all the flexibility of the standard. Table 3 summarizes the level of feature support.

Table 3. ADC14X250 Feature Support for the JESD204B Serial Interface

Feature Supported Not Supported
Subclass
  • Subclass 1
  • Subclass 0(1), 2
Device Clock
(CLKIN) and
SYSREF
  • AC coupled CLKIN and SYSREF
  • DC coupled CLKIN and SYSREF (special cases)
  • Periodic, Pulsed Periodic and One-Shot SYSREF
Latency
  • Deterministic latency supported for subclass 1 implementations using standard SYSREF signal
  • Deterministic latency not supported for non-standard implementations
Electrical layer features
  • LV-OIF-11G-SR interface and performance
  • AC coupled serial lanes
  • TX lane polarity inversion
  • DC coupled serial lanes
Transport layer features and configuration
  • L = 1
  • K configuration
  • Scrambling
  • F, S, and HD configuration depends on L and is not independently configurable
  • M, N, N’, CS, CF configuration
  • Idle link mode
  • Short and Long transport layer test patterns
Data link layer features
  • 8b/10b encoding
  • Lane synchronization
  • D21.5, K28.5, ILA, PRBS7, PRBS15, PRBS23, Ramp test sequences
  • RPAT/JSPAT test sequences
The ADC14X250 supports most subclass 0 requirements, but is not strictly subclass compliant.

Transport Layer Configuration

The transport layer features supported by the ADC14X250 device are a subset of possible features described in the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and most easy-to-use solution.

Lane Configuration

The ADC14X250 outputs all digital data on a single JESD204B serial lane. The serial-data lane transmits at 20 times the sampling rate. A 250 MSPS sampling rate corresponds to a 5.0 Gb/s per lane rate.

Frame Format

The format of the data arranged in a frame is fixed. The octets per frame (F), samples per frame (S), and high-density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters are fixed and not configurable. Figure 35 shows the data format.

ADC14X250 ADC14X250_Data_Format.gif Figure 35. Transport Layer Definitions for the Supported-Lane Configurations

ILA Information

Table 4 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of these parameters into the data stream is described in the JESD204B standard.

Table 4. Configuration of the JESD204B Serial-Data Receiver

Parameter Description Logical Value Encoded Value
ADJCNT DAC LMFC adjustment 0 0
ADJDIR DAC LMFC adjustment direction 0 0
BID Bank ID 0 0
CF Number of control words per frame clock period per link 0 0
CS Number of control bits per sample 0 0
DID Device identification number 0 0
F Number of octets per frame (per lane)(1) 2 1
HD High-density format 0 0
JESDV JESD204 version 1 1
K Number of frames per multi-frame(1) Set by register as 9 to 32 8 to 31
L Number of lanes per link(1) 1 0
LID Lane identification number 0 0
M Number of converters per device(1) 1 1
N Converter resolution (1) 16 15
N’ Total number of bits per sample(1) 16 15
PHADJ Phase adjustment request to DAC 0 0
S Number of samples per converter per frame cycle(1) 1 0
SCR Scrambling enabled Set by register as 0 (disabled) or 1 0 or 1
SUBCLASSV Device subclass version 1 1
RES1 Reserved field 1 0 0
RES2 Reserved field 2 0 0
FCHK Checksum 34 + (K-1) + SCR
These parameters have a binary-value-minus-1 encoding applied before being mapped into the link configuration octets. For example, F = 1 is encoded as 0.

Scrambling of the output serial data is supported and conforms to the JESD204B standard. Scrambling is disabled by default, but may be enabled via the SPI. When scrambling is enabled, the ADC14X250 device supports the early synchronization option by the receiver during the ILA sequence, although the ILA sequence data is never scrambled.

Test Pattern Sequences

The SPI may enable the following test pattern sequences. Short- and long-transport layer, RPAT, and JSPAT sequences are not supported.

Table 5. Supported Test Pattern Sequences

Test Pattern Description Common Purpose
D21.5 Alternating 1 and 0 pattern (101010...) Jitter or system debug
K28.5 Continuous K28.5 symbols System debug
Repeated ILA ILA repeats indefinitely System debug
Ramp After ILA, a sample ramp is transmitted with programmable step. The 16-bit output word fully spans both octets that compose a sample. System debug and transport layer verification
PRBS PRBS 7/15/23 Complies with ITU-T O.150 specification and is compatible with J-BERT equipment Jitter and bit error rate testing

JESD204B Link Initialization

A JESD204B link is established via link initialization, which involves the following steps: frame alignment, code group synchronization, and initial lane synchronization. These steps are shown in Figure 36. Link initialization must occur between the transmitting device (ADC14X250) and receiving device before sampled data may be transmitted over the link. The link initialization steps described here are specifically for the ADC14X250 device, supporting JESD204B subclass 1.

ADC14X250 JESD204_Synchronization_Timing.gif Figure 36. Link-initialization Timing and Flow Diagram

Frame Alignment

The Frame Alignment step requires alignment of the frame and local multi-frame clocks within the ADC14X250 device to an external reference. This is accomplished by providing the device clock and SYSREF clock to the CLKIN and SYSREF inputs, respectively. The ADC14X250 device aligns its frame clock and LMFC to any SYSREF rising edge event, offset by a SYSREF-to-LMFC propagation delay.

The SYSREF signal must be source synchronous to the device clock; therefore, the SYSREF rising edge must meet setup and hold requirements relative to the signal at the CLKIN input. If these requirements cannot be met, then the alignment of the internal frame and multi-frame clocks cannot be ensured. As a result, a link may still be established, but the latency through the link cannot be deterministic. Frame alignment may occur at any time; although, a re-alignment of the internal frame clock and LMFC will break the link. Note that frame alignment is not required for the ADC14X250 device to establish a link because the device automatically generates the clocks on power-up with unknown phase alignment.

Code Group Synchronization

Code Group Synchronization is initiated when the receiver sends a synchronization request by asserting the SYNCb input of the ADC14X250 device to a logic low state (SYNCb+ < SYNCb–). After the SYNCb assertion is detected, the ADC14X250 device outputs K28.5 symbols on all serial lanes that are used by the receiver to synchronize and time align its clock and data recovery (CDR) block to the known symbols. The SYNCb signal must be asserted for at least 4 frame clock cycles otherwise the event is ignored by the ADC14X250 device. Code group synchronization is completed when the receiver de-asserts the SYNCb signal to a logic high state.

After the ADC14X250 detects a de-assertion of its SYNCb input, the Initial Lane Synchronization step begins on the following LMFC boundary. The ADC14X250 device outputs 4 multi-frames of information that compose the ILA sequence. This sequence contains information about the data transmitted on the link. The initial lane synchronization step and link initialization conclude when the ILA is finished and immediately transitions into Data Transmission. During data transmission, valid sampled data is transmitted across the link until the link is broken.

ADC14X250 JESD204_Sychronization_Flow_Chart.gif Figure 37. Device Start-Up and JESD204B Link Synchronization Flow Chart

The flowchart in Figure 37 describes how the ADC14X250 device initializes the JESD204B link and reacts to changes in the link. After the ADC core calibration is finished, the ADC14X250 device begins with PLL calibration and link initialization using a default frame clock and LMFC alignment by sending K28.5 characters. PLL calibration requires approximately 153×103 sampling clock cycles. If SYNCb is not asserted, then the device immediately advances to the ILA sequence at the next LMFC boundary. Whereas, if SYNCb is asserted, then the device continues to output K28.5 characters until SYNCb is de-asserted.

When a SYSREF rising edge event is detected, then the ADC14X250 device compares the SYSREF event to the current alignment of the LMFC. If the SYSREF event is aligned to the current LMFC alignment, then no action is taken and the device continues to output data. If misalignment is detected, then the SYSREF event is compared to the frame clock. If misalignment of the frame clock is also detected, then the clocks are re-aligned and the link is re-initialized. If the frame clock is not misaligned, then the frame clock alignment is not updated. In the cases that a SYSREF event causes a link re-initialization, the ADC14X250 device begins sending K28.5 characters without a SYNCb assertion and immediately transitions to the ILA sequence on the next LMFC boundary unless the SYNCb signal is asserted. Anytime the frame clock and LMFC are re-aligned, the serializer PLL must calibrate before code group synchronization begins. SYSREF events must not occur during ADC14X250 device power-up, ADC calibration, or PLL calibration. The JESD_STATUS register is available to check the status of the ADC14X250 device and the JESD204B link.

If a SYNCb assertion is detected for at least 4 frame clock cycles, the ADC14X250 device immediately breaks the link and sends K28.5 characters until the SYNCb signal is de-asserted.

When exiting sleep mode, the frame clock and LMFC are started with a default (unknown) phase alignment, PLL calibration is performed, and the device immediately transitions into sending K28.5 characters.

Sync~ Signal Selection

The JESD204B sync~ signal can be directed to the internal JESD204B core block via two different input paths: via the external pins or SPI. The selection MUX is controlled using the SYNC_SEL register field and sync~ control is performed using the JSYNC_N register field via SPI . By default, the signal is routed from the external SYNCb+/- pins and writes to the JSYNC_N register field are ignored.

Optionally, the signal may be routed via SPI by setting the register field SYNC_SEL = 1. In this mode, signals at the external SYNCb+/- pins are ignored and the sync~ signal is written to the JSYNC_N register field.

SPI

The SPI allows access to the internal configuration registers of the ADC through read and write commands to a specific address. The interface protocol has a 1-bit command, 15-bit address word and 8-bit data word as shown in Figure 38. A read or write command is 24 bits in total, starting with the read or write command bit where 0 indicates a write command and 1 indicates a read command. The read or write command bit is clocked into the device on the first rising edge of SCLK after CSb is asserted to 0. During a write command, the 15-bit address and 8-bit data values follow the read or write bit MSB-first and are latched on the rising edge of SCLK. During a read command, the SDO output is enabled shortly after the 16th rising edge of SCLK and outputs the read value MSB first before the SDO output is returned to a high impedance state. The read or write command is completed on the SCLK rising edge on which the data word’s LSB is latched. CSb may be de-asserted to 1 after the LSB is latched into the device.

The SPI allows command streaming where multiple commands are made without de-asserting CSb in-between commands. The commands in the stream must be of similar types, either read or write. Each subsequent command applies to the register address adjacent to the register accessed in the previous command. The address order can be configured as either ascending or descending. Command streaming is accomplished by immediately following a completed command with another set of 8 rising edges of SCLK without de-asserting CSb. During a write command, an 8-bit data word is input on the SDI input for each subsequent set of SCLK edges. During a read command, data is output from SDO for each subsequent set of SCLK edges. Each subsequent command is considered finished after the 8th rising edge of SCLK. De-asserting CSb aborts an incomplete command.

The SDO output is high impedance at all times other than during the final portion of a read command. During the time that the SDO output is active, the logic level is determined by a configuration register. The SPI output logic level must be properly configured after power up and before making a read command to prevent damaging the receiving device or any other device connected to the SPI bus. Until the SPI_CFG register is properly configured, voltages on the SDO output may be as high as the VA3.0 supply during a read command. The default state of SDO is to output 3 V logic levels during a read command. The SDI, SCLK, and CSB pins are all 1.2-V to 3-V logic compatible.

ADC14X250 SPI_Protocol_Diagram.gif Figure 38. Serial Interface Protocol

Device Functional Modes

Power-Down and Sleep Modes

Power-down and sleep modes are provided to allow the user to reduce the power consumption of the device without disabling power supplies. Both modes reduce power consumption by the same amount but they differ in the amount of time required to return to normal operation. Upon changing from Power Down back to Normal operation, an ADC calibration routine is performed. Waking from sleep mode does not perform ADC calibration (see ADC Core Calibration for more details). Neither power-down mode nor sleep mode resets configuration registers.

Register Map

Table 6. ADC14X250 Register Map

Register ADDRESS DFLT b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0]
CONFIG_A 0x0000 0x3C SR Res (0) ASCEND Res (1) PAL[3:0]
Address 0x0001 Reserved
DEVICE _CONFIG 0x0002 0x00 Reserved (000000) PD_MODE[1:0]
CHIP_TYPE 0x0003 0x03 Reserved (0000) CHIP_TYPE[3:0]
CHIP_ID 0x0004 0x01 CHIP_ID[7:0]
0x0005 0x00 CHIP_ID[15:8]
CHIP _VER 0x0006 0x00 CHIP_VER[7:0]
Address 0x0007-0x000B Reserved
VENDOR_ID 0x000C 0x51 VENDOR_ID[7:0]
0x000D 0x04 VENDOR_ID[15:8]
SPI_CFG 0x0010 0x01 Reserved (000000) VSPI[1:0]
OM1 0x0012 0x81 DF Res (00) IDLE[1:0] SYS_EN Res(01)
OM2 0x0013 0x20 Reserved (001) CLKDIV Res (0) Res (0) Res (0)
IMB_ADJ 0x0014 0x00 Res (0) AMPADJ[2:0] PHADJ[3:0]
Address 0x0015-0x003C Reserved
DC_MODE 0x003D 0x00 Reserved (00000) DC_TC DC_EN
Address 0x003E-0x0046 Reserved
SER_CFG 0x0047 0x00 Res(0) VOD[2:0] Res (0) DEM[2:0]
Address 0x0048-0x005F Reserved
JESD_CTRL1 0x0060 0x7D SCR _EN K_M1[4:0] Res (0) JESD _EN
JESD_CTRL2 0x0061 0x00 SYNC_SEL JSYNC_N Reserved (00) JESD_TEST_MODE[3:0]
JESD_RSTEP 0x0062 0x01 JESD_RSTEP[7:0]
0x0063 0x00 JESD_RSTEP[15:8]
Address 0x0064-0x006B Reserved
JESD_STATUS 0x006C N/A Res (0) LINK SYNC REALIGN ALIGN PLL _LOCK CAL _DONE CLK _RDY
Address 0x006D- Reserved

Register Descriptions

CONFIG_A, [Address: 0x0000], [Default: 0x3C]

Table 7. CONFIG_A, [Address: 0x0000], [Default: 0x3C]

Bit Field Type Reset Description
7 SR Read or write 0 Setting this soft reset bit causes all registers to be reset to their default state. This bit is self-clearing.
6 Reserved Read or write 0 Reserved and must be written with 0.
5 ASCEND Read or write 1 Order of address change during streaming reads or writes.
0 : Address is decremented during streaming reads or writes.
1 : Address is incremented during streaming reads or writes (default).
4 Reserved Read 1 Reserved and must be written with 1.
3:0 PAL[3:0] Read or write 1100 Palindrome Bits are bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, and bit 0 = bit 7.

DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]

Table 8. DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]

Bit Field Type Reset Description
[7:2] Reserved Read or write 000000 Reserved and must be written with 000000.
[1:0] PD_MODE [1:0] Read or write 00 Power-down mode
00 : Normal operation (default)
01 : Reserved
10 : Sleep operation (faster resume)
11 : Power-down (slower resume)

CHIP_TYPE, [Address: 0x0003], [Default: 0x03]

Table 9. CHIP_TYPE, [Address: 0x0003], [Default: 0x03]

Bit Field Type Reset Description
[7:4] Reserved Read or write 0000 Reserved and must be written with 0000.
[3:0] CHIP_TYPE Read 0011 Chip type that always returns 0x3, indicating that the part is a high-speed ADC

CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]

Table 10. CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]

Bit Field Type Reset Description
0x0004[7:0] CHIP_ID[7:0] Read 0x01 Chip ID least significant word
0x0005[7:0] CHIP_ID[15:8] Read 0x00 Chip ID most significant word

CHIP_VERSION, [Address: 0x0006], [Default: 0x00]

Table 11. CHIP_VERSION, [Address: 0x0006], [Default: 0x00]

Bit Field Type Reset Description
[7:0] CHIP_VER Read 0x00 Chip version

VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]

Table 12. VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]

Bit Field Type Reset Description
0x000C[7:0] VENDOR_ID
[7:0]
Read 0x51 Vendor ID. Texas Instruments vendor ID is 0x0451.
0x000D[7:0] VENDOR_ID
[15:8]
Read 0x04

SPI_CFG, [Address: 0x0010], [Default: 0x01]

Table 13. SPI_CFG, [Address: 0x0010], [Default: 0x01]

Bit Field Type Reset Description
[7:2] Reserved Read or write 000000 Reserved and must be written with 000000.
[1:0] VSPI Read or write 01 SPI logic level controls the SDO output logic level.
00 : 1.2 V
01 : 3.0 V (default)
10 : 2.5 V
11 : 1.8 V
This register must be configured (written) before making a read command on the SPI bus if the logic level is different that the VSPI setting. The SPI inputs (SDI, SCLK, and CSb) are compatible with logic levels ranging from 1.2 to 3 V.

OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]

Table 14. OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]

Bit Field Type Reset Description
[7] DF Read or write 1 Output data format
0 : Offset binary
1 : Signed 2s complement (default)
[6:5] Reserved Read or write 00 Reserved and must be written with 00.
[4:3] IDLE[1:0] Read or write 00 SYSREF idle state offset configuration.
00 : No offset applied (default)
01 : SYSREF idles low (de-asserted) with –400-mV offset
10 : SYSREF idles high (asserted) with +400-mV offset
11 : Reserved
[2] SYS_EN Read or write 0 SYSREF detection gate enable
0 : SYSREF gate is disabled; (input is ignored, default)
1 : SYSREF gate is enabled
[1:0] Reserved[1:0] Read or write 01 Reserved. Must be written with 01.

OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]

Table 15. OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]

Bit Field Type Reset Description
[7:5] Reserved Read or write 001 Reserved and must be written with 001.
[4:3] CLKDIV[1:0] Read or write 00 Clock divider ratio. Sets the value of the clock divide factor, CLKDIV
00 : Divide by 1, CLKDIV = 1 (default)
01 : Divide by 2, CLKDIV = 2
10 : Divide by 4, CLKDIV = 4
11 : Divide by 8, CLKDIV = 8
[2:0] Reserved Read or write 000 Reserved. Must be written with 000.

IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]

Table 16. IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]

Bit Field Type Reset Description
[7] Reserved Read or write 0 Reserved. Must be written with 0.
[6:4] AMPADJ[2:0] Read or write 000 Analog input amplitude imbalance correction
7 = +30 Ω VIN+, –30 Ω VIN–
6 = +20 Ω VIN+, –20 Ω VIN–
5 = +10 Ω VIN+, –10 Ω VIN–
4 = Reserved
3 = –30 Ω VIN+, +30 Ω VIN–
2 = –20 Ω VIN+, +20 Ω VIN–
1 = –10 Ω VIN+, +10 Ω VIN–
0 = +0 Ω VIN+, –0 Ω VIN– (default)
Resistance changes indicate variation of the internal single-ended termination.
[3:0] PHADJ[3:0] Read or write 0000 Analog input phase imbalance correction
15 = +1.68 pF VIN–
...
9 = +0.48 pF VIN–
8 = +0.24 pF VIN–
7 = +1.68 pF VIN+
...
2 = +0.48 pF VIN+
1 = +0.24 pF VIN+
0 = +0 pF VIN+, +0 pF VIN– (default)
Capacitance changes indicate the addition of internal capacitive load on the given pin.

DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]

Table 17. DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]

DC_MODE (DC Offset Correction Mode)
Bit Field Type Reset Description
[7:3] Reserved Read or write 00000 Reserved and must be written as 00000.
[2:1] TC_DC Read or write 00 DC offset filter time constant.
The time constant determines the filter bandwidth of the DC high-pass filter.
TC_DC Time Constant (FS = 250 MSPS) 3-dB Bandwidth (FS = 250 MSPS) 3-dB Bandwidth (Normalized)
00 17 µs 9.3 kHz 37e–6 × Fs
01 130 µs 1.2 kHz 4.9e–6 × Fs
10 1.1 ms 150 Hz 605e–9 × Fs
11 8.4 ms 19 Hz 76e–9 × Fs
[0] DC_EN Read or Write 0 DC offset correction enable
0 : Disable DC offset correction
1 : Enable DC offset correction

SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]

Table 18. SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]

Bit Field Type Reset Description
[7] Reserved Read or write 0 Reserved. Must be written as 0.
[6:4] VOD[2:0] Read or write 000 Serial-lane transmitter driver output differential peak-peak-voltage amplitude.
000 : 0.570 V (default)
001 : 0.660 V
010 : 0.750 V
011 : 0.840 V
100 : 0.940 V
101 : 1.02 V
110 : 1.11 V
111 : 1.20 V
Reported voltage values are nominal values at low-lane rates with de-emphasis disabled
[3] Reserved Read or write 0 Reserved and must be written as 0.
[2:0] DEM[2:0] Read or write 000 Serial lane transmitted de-emphasis.
De-emphasis value are for VOD configured to 100.
DEM De-emphasis [dB]
000 0.0
001 1.4
010 3.4
011 4.9
100 5.9
101 7.4
110 8.9
111 12.1

JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]

Table 19. JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]

Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not supported.
Bit Field Type Reset Description
[7] SCR_EN Read or write 0 Scrambler enable.
0 : Disabled (default)
1 : Enabled
Note:
  • JESD_EN must be set to 0 before altering this field.
[6:2] K_M1[4:0] Read or write 11111 Number of frames per multi-frame, K – 1.
The binary values of K_M1 represent the value (K – 1)
00000 : Reserved
00001 : Reserved

00111 : Reserved
01000 : K = 9

11111 : K = 32 (default)
Note:
  • K must be in the range 9 to 32. Values outside this range are either reserved or may produce unexpected results.
  • JESD_EN must be set to 0 before altering this field.
[1] Reserved Read or write 0 Reserved and must be written as 0.
[0] JESD_EN Read or write 1 JESD204B link enable.
When enabled, the JESD204B link synchronizes and transfers data normally. When the link is disabled, the serial transmitters output a repeating, alternating 01010101 stream.
0 : Disabled
1 : Enabled (default)

JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]

Table 20. JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]

Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not supported.
Bit Field Type Reset Description
[7] SYNC_SEL Read or write 0 SYNCb Signal MUX Select
0 : The internal SYNCb signal is routed from the SYNCb+/- pins (default)
1 : The internal SYNCb signal is routed from the JSYNC_N register field (SYNCb over SPI)
[6] JSYNC_N Read or write 0 SYNCb Over SPI Control
0 : The internal SYNCb signal as asserted, indicating a JESD204 link synchronization request (default)
1 : The internal SYNCb signal is de-asserted, indicating JESD204 link synchronization is not being requested
Note: JSYNC_N controls the internal SYNCb signal only when SYNC_SEL = 1. When SYNC_SEL = 0, this register field is ignored.
[7:4] Reserved Read or write 00 Reserved. Must be written as 00.
[3:0] JESD_TEST_MODES[3:0] Read or write 0000 JESD204B test modes.
0000 : Test mode disabled. Normal operation (default)
0001 : PRBS7 test mode
0010 : PRBS15 test mode
0011 : PRBS23 test mode
0100 : RESERVED
0101 : ILA test mode
0110 : Ramp test mode
0111 : K28.5 test mode
1000 : D21.5 test mode
1001: Logic low test mode (serial outputs held low)
1010: Logic high test mode (serial outputs held high)
1011 – 1111 : Reserved
Note:
  • JESD_EN must be set to 0 before altering this field.

JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]

Table 21. JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]

Bit Field Type Reset Description
0x0062[7:0] JESD_RSTEP
[7:0]
Read or write 0x01 JESD204B ramp test mode step
0x0063[7:0] JESD_RSTEP
[15:8]
Read or write 0x00 The binary value JESD_RSTEP[15:0] corresponds to the step of the ramp mode step. A value of 0x0000 is not allowed.
Note:
  • JESD_EN must be set to 0 before altering this field.

JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]

Table 22. JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]

Bit Field Type Reset Description
[7] Reserved Read N/A Reserved.
[6] LINK Read N/A JESD204B link status
This bit is set when synchronization is finished, transmission of the ILA sequence is complete, and valid data is being transmitted.
0 : Link not established
1 : Link established and valid data transmitted
[5] SYNC Read N/A JESD204B link synchronization request status
This bit is cleared when a synchronization request is received at the SYNCb input.
0 : Synchronization request received at the SYNCb input and synchronization is in progress
1 : Synchronization not requested
Note:
  • SYNCb must be asserted for at least four local frame clocks before synchronization is initiated. The SYNC status bit reports the status of synchronization, but does not necessarily report the current status of the signal at the SYNCb input.
[4] REALIGN Read or write N/A SYSREF re-alignment status
This bit is set when a SYSREF event causes a shift in the phase of the internal frame or LMFC clocks.
Note:
  • Write a 1 to REALIGN to clear the bit field to a 0 state.
  • SYSREF events that do not cause a frame or LMFC clock phase adjustment do not set this register bit.
  • If CLK_RDY becomes low, this bit is cleared.
[3] ALIGN Read or write N/A SYSREF alignment status
This bit is set when the ADC has processed a SYSREF event and indicates that the local frame and multi-frame clocks are now based on a SYSREF event.
Note:
  • Write a 1 to ALIGN to clear the bit field to a 0 state.
  • Rising-edge SYSREF event sets ALIGN bit.
  • If CLK_RDY becomes low, this bit is cleared.
[2] PLL_LOCK Read N/A PLL lock status. This bit is set when the PLL has achieved lock.
0 : PLL unlocked
1 : PLL locked
[1] CAL_DONE Read N/A ADC calibration status
This bit is set when the ADC calibration is complete.
0 : Calibration currently in progress or not yet completed
1 : Calibration complete
Note:
  • Calibration must complete before SYSREF detection (SYS_EN) can be enabled.
  • Calibration must complete before the any clock phase delay adjustments are made.
[0] CLK_RDY Read N/A Input clock status
This bit is set when the ADC is powered-up and detects an active clock signal at the CLKIN input.
0 : CLKIN not detected
1 : CLKIN detected