9.3.13.2 Code Group Synchronization

Code Group Synchronization is initiated when the receiver sends a synchronization request by asserting the SYNCb input of the ADC31JB68 device to a logic low state (SYNCb+ < SYNCb–). After the SYNCb assertion is detected, the ADC31JB68 device outputs K28.5 symbols on all serial lanes. These symbols are used by the receiver to synchronize and time align its clock and data recovery (CDR) block to the known symbols. The SYNCb signal must be asserted for at least 4 frame clock cycles otherwise the event is ignored by the ADC31JB68 device. Code group synchronization is completed when the receiver de-asserts the SYNCb signal to a logic high state.

After the ADC31JB68 detects a de-assertion of its SYNCb input, the Initial Lane Synchronization step begins on the following LMFC boundary. The ADC31JB68 device outputs 4 multi-frames of information that compose the ILA sequence. This sequence contains information about the data transmitted on the link. The initial lane synchronization step and link initialization conclude when the ILA is finished and immediately transitions into Data Transmission. During data transmission, valid sampled data is transmitted across the link until the link is broken.

Figure 36. Device Start-Up and JESD204B Link Synchronization Flow Chart

The flowchart in Figure 36 describes how the ADC31JB68 device initializes the JESD204B link and reacts to changes in the link. After the ADC core calibration is finished, the ADC31JB68 device begins with PLL calibration and link initialization using a default frame clock and LMFC alignment by sending K28.5 characters. PLL calibration requires approximately 153×10³ sampling clock cycles. If SYNCb is not asserted, then the device immediately advances to the ILA sequence at the next LMFC boundary. If SYNCb is asserted, then the device continues to output K28.5 characters until SYNCb is de-asserted.

When a SYSREF rising edge event is detected, then the ADC31JB68 device compares the SYSREF event to the current alignment of the LMFC. If the SYSREF event is aligned to the current LMFC alignment, then no action is taken and the device continues to output data. If misalignment is detected, then the SYSREF event is compared to the frame clock. If misalignment of the frame clock is also detected, then the clocks are re-aligned and the link is reinitialized. If the frame clock is not misaligned, then the frame clock alignment is not updated. In the cases that a SYSREF event causes a link re-initialization, the ADC31JB68 device begins sending K28.5 characters without a SYNCb assertion and immediately transitions to the ILA sequence on the next LMFC boundary unless the SYNCb signal is asserted. Anytime the frame clock and LMFC are re-aligned, the serializer PLL must calibrate before code group synchronization begins. SYSREF events must not occur during ADC31JB68 device power-up, ADC calibration, or PLL calibration. The JESD_STATUS register is available to check the status of the ADC31JB68 device and the JESD204B link.

If a SYNCb assertion is detected for at least 4 frame clock cycles, the ADC31JB68 device immediately breaks the link and sends K28.5 characters until the SYNCb signal is de-asserted.

When exiting sleep mode, the frame clock and LMFC are started with a default (unknown) phase alignment, PLL calibration is performed, and the device immediately transitions into sending K28.5 characters.