JAJSGV3B September   2015  – January 2019 ADC31JB68

PRODUCTION DATA.  

  1. 1 特長
    1. 18 インチ / 5mil のFR4 マイクロストリップ・トレース出力の送信アイ、5Gb/s 時、ディエンファシスを最適化済み
  2. 2 アプリケーション
  3. 3 概要
    1.     -1dBFS、450MHz 入力でのスペクトル
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Converter Performance
    6. 7.6 Electrical Characteristics: Power Supply
    7. 7.7 Electrical Characteristics: Interface
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Interface Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs and Input Buffer
      2. 9.3.2  Amplitude and Phase Imbalance Correction
      3. 9.3.3  Over-Range Detection
      4. 9.3.4  Input Clock Divider
      5. 9.3.5  SYSREF Detection Gate
      6. 9.3.6  Serial Differential Output Drivers
        1. 9.3.6.1 De-Emphasis Equalization
        2. 9.3.6.2 Serial Lane Inversion
      7. 9.3.7  ADC Core Calibration
      8. 9.3.8  Data Format
      9. 9.3.9  JESD204B Supported Features
      10. 9.3.10 JESD204B Interface
      11. 9.3.11 Transport Layer Configuration
        1. 9.3.11.1 Lane Configuration
        2. 9.3.11.2 Frame Format
        3. 9.3.11.3 ILA Information
      12. 9.3.12 Test Pattern Sequences
      13. 9.3.13 JESD204B Link Initialization
        1. 9.3.13.1 Frame Alignment
        2. 9.3.13.2 Code Group Synchronization
      14. 9.3.14 SPI
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down and Sleep Modes
    5. 9.5 Register Map
      1. 9.5.1 Register Descriptions
        1. 9.5.1.1  CONFIG_A (address = 0x0000) [reset = 0x3C]
          1. Table 6. CONFIG_A
        2. 9.5.1.2  DEVICE CONFIG (address = 0x0002) [reset = 0x00]
          1. Table 7. DEVICE CONFIG
        3. 9.5.1.3  CHIP_TYPE (address = 0x0003 ) [reset = 0x03]
          1. Table 8. CHIP_TYPE
        4. 9.5.1.4  CHIP_ID (address = 0x0005, 0x0004) [reset = 0x00, 0x1B]
          1. Table 9. CHIP_ID
        5. 9.5.1.5  CHIP_VERSION (address =0x0006) [reset = 0x00]
          1. Table 10. CHIP_VERSION
        6. 9.5.1.6  VENDOR_ID (address = 0x000D, 0x000C) [reset = 0x04, 0x51]
          1. Table 11. VENDOR_ID
        7. 9.5.1.7  SPI_CFG (address = 0x0010 ) [reset = 0x01]
          1. Table 12. SPI_CFG
        8. 9.5.1.8  OM1 (Operational Mode 1) (address = 0x0012) [reset = 0xC1]
          1. Table 13. OM1 (Operational Mode 1)
        9. 9.5.1.9  OM2 (Operational Mode 2) (address = 0x0013) [reset = 0x20]
          1. Table 14. OM2 (Operational Mode 2)
        10. 9.5.1.10 IMB_ADJ (Imbalance Adjust) (address = 0x0014) [reset = 0x00]
          1. Table 15. IMB_ADJ (Imbalance Adjust)
        11. 9.5.1.11 OVR_EN (Over-Range Enable) (address = 0x003A) [reset = 0x00]
          1. Table 16. OVR_EN (Over-Range Enable)
        12. 9.5.1.12 OVR_HOLD (Over-Range Hold) (address = 0x003B) [reset = 0x00]
          1. Table 17. OVR_HOLD (Over-Range Hold)
        13. 9.5.1.13 OVR_TH (Over-Range Threshold) (address = 0x003C) [reset = 0x00]
          1. Table 18. OVR_TH (Over-Range Threshold)
        14. 9.5.1.14 DC_MODE (DC Offset Correction Mode) (address = 0x003D) [reset = 0x00]
          1. Table 19. DC_MODE (DC Offset Correction Mode)
        15. 9.5.1.15 SER_CFG (Serial Lane Transmitter Configuration) (address = 0x0047) [reset = 0x00]
          1. Table 20. SER_CFG (Serial Lane Transmitter Configuration)
        16. 9.5.1.16 JESD_CTRL1 (JESD Configuration Control 1) (address = 0x0060) [reset = 0x7F]
          1. Table 21. JESD_CTRL1 (JESD Configuration Control 1)
        17. 9.5.1.17 JESD_CTRL2 (JESD Configuration Control 2) (address = 0x0061) [reset = 0x00]
          1. Table 22. JESD_CTRL2 (JESD Configuration Control 2)
        18. 9.5.1.18 JESD_RSTEP (JESD Ramp Pattern Step) (address = 0x0063, 0x0062) [reset = 0x00, 0x01]
          1. Table 23. JESD_RSTEP (JESD Ramp Pattern Step)
        19. 9.5.1.19 SER_INV (Serial Lane Inversion Control) (address = 0x0064) [reset = 0x00]
          1. Table 24. SER_INV (Serial Lane Inversion Control)
        20. 9.5.1.20 JESD_STATUS (JESD Link Status) (address = 0x006C) [reset = N/A]
          1. Table 25. JESD_STATUS (JESD Link Status)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Optimizing Converter Performance
        1. 10.1.1.1 Internal Noise Sources
        2. 10.1.1.2 External Noise Sources
      2. 10.1.2 Analog Input Considerations
        1. 10.1.2.1 Differential Analog Inputs and Full Scale Range
        2. 10.1.2.2 Analog Input Network Model
        3. 10.1.2.3 Input Bandwidth
        4. 10.1.2.4 Driving the Analog Input
        5. 10.1.2.5 Clipping and Over-Range
      3. 10.1.3 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 10.1.3.1 Driving the CLKIN+ and CLKIN– Input
        2. 10.1.3.2 Driving the SYSREF Input
        3. 10.1.3.3 SYSREF Signaling
        4. 10.1.3.4 SYSREF Timing
        5. 10.1.3.5 Effectively Using the Detection Gate Feature
        6. 10.1.3.6 Driving the SYNCb Input
      4. 10.1.4 Output Serial Interface Considerations
        1. 10.1.4.1 Output Serial-Lane Interface
        2. 10.1.4.2 Voltage Swing and De-Emphasis Optimization
        3. 10.1.4.3 Minimizing EMI
      5. 10.1.5 JESD204B System Considerations
        1. 10.1.5.1 Frame and LMFC Clock Alignment Procedure
        2. 10.1.5.2 Link Interruption
        3. 10.1.5.3 Clock Configuration Examples
      6. 10.1.6 SPI
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Design
    2. 11.2 Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

The ADC31JB68 is packaged in a 40-pin QFN package (6 x 6 x 0.8, 0.5 mm pin-pitch) with a bottom-side exposed paddle.

RTA Package
40 PIN (WQFN)
Top View
ADC31JB68 Device_Pinout.gif

Pin Functions

PIN TYPE or DIAGRAM DESCRIPTION
NAME NO.
INPUT/REFERENCE
VIN+
VIN–		 4, 5
ADC31JB68 pin_VIN_VCM.gif
Differential analog input pins.
The differential full-scale signal level is 1.7 Vpp. Each input pin is terminated to the internal 1.6V common-mode reference with a 100 Ω resistor for a 200 Ω total differential termination.
VCM 7 Input Interface Common mode voltage.
This pin must be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor that is placed as close to the pin as possible to minimize stray inductance. A 10 µF capacitor should also be placed in parallel. It is recommended to use VCM to provide the common mode voltage for the differential analog inputs. The input common-mode bias is provided internally for the ADC input, therefore external use of VCM is recommended but not strictly required. The recommended decoupling is always required.
CLOCK/SYNC
CLKIN+
CLKIN–		 11, 12
ADC31JB68 pin_CLKIN.gif
Differential device clock input pins.
AC coupling is recommended for coupling the clock input to these pins. DC biasing of the clock receiver is provided internally. Each pin is internally terminated to the 500mV DC bias with 50 Ω resistor for a 100 Ω total internal differential termination resistor. Sampling occurs on the falling edge of the differential signal (CLKIN+) − (CLKIN-).
SYSREF+,
SYSREF–		 17, 18 ADC31JB68 pin_SYSREF.gif Differential SYSREF signal input pins.
Each pin is internally terminated to the DC bias with a large resistor. An internal 100 Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYSREF input a wide input common mode range.
SYNCb+
SYNCb–		 19, 20 ADC31JB68 pin_SYNC.gif Differential SYNCb signal input pins.
DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100 Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common mode range. The SYNCb signal is active low and is therefore asserted when the voltage at SYNCb+ is less than at SYNCb–.
SERIAL INTERFACE (SPI)
SCLK 32 ADC31JB68 pin_SDI_CSb_SCLK.gif SPI Interface Serial Clock pin.
Serial data is shifted into and out of the device synchronous with this clock signal. Compatible with 1.2–3.0V CMOS logic levels.
CSB 31 SPI Interface Chip Select pin.
When this signal is asserted, SCLK is used to clock input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is high impedance and the input data is ignored. Active low. A 1kΩ pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2–3.0V CMOS logic levels.
SDI 33 SPI Interface Data Input pin.
Serial data is shifted into the device on this pin while the CSB signal is asserted. Compatible with 1.2-3.0V CMOS logic levels.
SDO/OVR 34 ADC31JB68 pin_SDO_OVR.gif SPI Data Output and Over-Range pin.
Dual mode pin. When configured as SDO, serial data of the SPI is shifted out of the device on this pin while CSB is asserted. When configured as OVR, the over-range signal is output. Pin mode configurable via the SPI. Output voltage is configurable to 1.2V, 1.8V, or 3.0V CMOS logic levels via the SPI. Default configuration outputs the SDO at a 1.8V logic level.
DIGITAL OUTPUT INTERFACE
SO0+, SO0–,
SO1+, SO1–		 25, 26,
23, 24		 ADC31JB68 pin_S0.gif Differential High Speed Serial Data Lane pins.
These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100 Ω characteristic impedance.
POWER SUPPLY
VA3.0 1, 2 Supply Input Pin 3 V Analog Power Supply pin.
This pin must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer.
VA1.8 15, 16, 28, 39, 40 Supply Input Pin 1.8 V Analog Power Supply pins.
These pins must be connected to a quiet source and decoupled to AGND with a
0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer.
VA1.2 21, 29, 35, 36 Supply Input Pin 1.2 V Analog Power Supply pins.
These pins must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer.
VACLK1.2 8, 9 Supply Input Pin 1.2 V Analog Power Supply pins for internal clock path.
These pins must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer.
AGND 3, 6, 10, 13, 14, 22, 27, 30, 37, 38 Analog Ground Analog Ground.
Solid ground reference planes under the device are recommended.
Exposed Thermal Pad Exposed Thermal Pad.
The exposed pad must be connected to the AGND ground plane electrically and with good thermal dissipation properties to ensure rated performance.