9.3.1 Analog Inputs

The ADC324x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC324x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 136, Figure 137, and Figure 138. See Figure 139 for details regarding the internal clock buffer.

NOTE: R_T = termination resistor, if necessary.

Figure 136. Differential Sine-Wave Clock Driving Circuit

Figure 137. LVDS Clock Driving Circuit

Figure 138. LVPECL Clock Driving Circuit

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 139. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 140. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 140. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies.

Equation 1.

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.

Equation 2.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. T_Jitter can be calculated with Equation 3.

Equation 3.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC324x has a typical thermal noise of 73.5 dBFS and internal aperture jitter of 130 fs. Figure 141 shows SNR (from 1 MHz offset leaving the 1/f flicker noise) for different jitter of clock driver.

Figure 141. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using the serial interface, as shown in Table 3. The output interface options are:

• One-wire, 1x frame clock, 14x serialization with the DDR bit clock and
• Two-wire, 0.5x frame clock, 7x serialization with the DDR bit clock.

9.3.3.2 Two-Wire Interface: 7x Serialization

The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as shown in Figure 142. Note that in two-wire mode, the frame clock (FCLK) frequency is half of sampling clock (CLKIN) frequency.

Figure 142. Output Timing Diagram

9.4.1 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to f_S / 2. Figure 143 shows the noise spectrum with the chopper off and Figure 144 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at f_S / 2 that must be filtered out digitally.

fIN = 10 MHz, fS = 125 MHz

Figure 143. Chopper Off

fIN = 10 MHz, fS = 125 MHz

Figure 144. Chopper On

9.4.3 Power-Down Control

The power-down functions of the ADC324x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality, as shown in Table 4.

9.4.4 Internal Dither Algorithm

The ADC324x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 145 and Figure 146 show the effect of using dither algorithms.

SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS, THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc

Figure 145. FFT with Dither On

SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS, THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc

Figure 146. FFT with Dither Off

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 147. If required, the serial interface registers can be cleared during operation either:

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 147 and Table 6 show the timing requirements for the serial register write operation.

Figure 147. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

		MIN	TYP	MAX	UNIT
fSCLK	SCLK frequency (equal to 1 / tSCLK)	> dc		20	MHz
tSLOADS	SEN to SCLK setup time	25			ns
tSLOADH	SCLK to SEN hold time	25			ns
tDSU	SDIO setup time	25			ns
tDH	SDIO hold time	25			ns

(1) Typical values are at 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted.

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. Given below is the procedure to read contents of serial registers:

1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 148 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 149.

Figure 148. Serial Register Read Timing Diagram

Figure 149. SDOUT Timing Diagram

9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 150 and Table 7.

Figure 150. Initialization of Serial Registers after Power-Up

If required, the serial interface registers can be cleared during operation either:

1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

Table 8. Register Map Summary

9.6.1 Summary of Special Mode Registers

Table 9 lists the location, value, and functions of special mode registers in the device.

9.6.2 Serial Register Description