SBAS668A May   2014  – June 2015 ADC32J22 , ADC32J23 , ADC32J24 , ADC32J25

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: ADC32J22, ADC32J23
    7. 7.7  Electrical Characteristics: ADC32J24, ADC32J25
    8. 7.8  AC Performance: ADC32J25
    9. 7.9  AC Performance: ADC32J24
    10. 7.10 AC Performance: ADC32J23
    11. 7.11 AC Performance: ADC32J22
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements
    14. 7.14 Typical Characteristics: ADC32J25
    15. 7.15 Typical Characteristics: ADC32J24
    16. 7.16 Typical Characteristics: ADC32J23
    17. 7.17 Typical Characteristics: ADC32J22
    18. 7.18 Typical Characteristics: Common Plots
    19. 7.19 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Descriptions
        1. 9.6.2.1  Register 01h (address = 01h)
        2. 9.6.2.2  Register 03h (address = 03h)
        3. 9.6.2.3  Register 04h (address = 04h)
        4. 9.6.2.4  Register 06h (address = 06h)
        5. 9.6.2.5  Register 07h (address = 07h)
        6. 9.6.2.6  Register 08h (address = 08h)
        7. 9.6.2.7  Register 09h (address = 09h)
        8. 9.6.2.8  Register 0Ah (address = 0Ah)
        9. 9.6.2.9  Register 0Bh (address = 0Bh)
        10. 9.6.2.10 Register 0Ch (address = 0Ch)
        11. 9.6.2.11 Register 0Dh (address = 0Dh)
        12. 9.6.2.12 Register 0Eh (address = 0Eh)
        13. 9.6.2.13 Register 0Fh (address = 0Fh)
        14. 9.6.2.14 Register 13h (address = 13h)
        15. 9.6.2.15 Register 15h (address = 15h)
        16. 9.6.2.16 Register 27h (address = 27h)
        17. 9.6.2.17 Register 2Ah (address = 2Ah)
        18. 9.6.2.18 Register 2Bh (address = 2Bh)
        19. 9.6.2.19 Register 2Fh (address = 2Fh)
        20. 9.6.2.20 Register 30h (address = 30h)
        21. 9.6.2.21 Register 31h (address = 31h)
        22. 9.6.2.22 Register 34h (address = 34h)
        23. 9.6.2.23 Register 3Ah (address = 3Ah)
        24. 9.6.2.24 Register 3Bh (address = 3Bh)
        25. 9.6.2.25 Register 3Ch (address = 3Ch)
        26. 9.6.2.26 Register 422h (address = 422h)
        27. 9.6.2.27 Register 434h (address = 434h)
        28. 9.6.2.28 Register 522h (address = 522h)
        29. 9.6.2.29 Register 534 (address = 534h)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
ADC32J22 ADC32J23 ADC32J24 ADC32J25 PO_BAS663.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD 4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46 I Analog 1.8-V power supply
CLKM 18 I Negative differential clock input for the ADC
CLKP 19 I Positive differential clock input for the ADC
DAM 48 O Negative serial JESD204B output for channel A
DAP 47 O Positive serial JESD204B output for channel A
DBM 45 O Negative serial JESD204B output for channel B
DBP 44 O Positive serial JESD204B output for channel B
DVDD 3,34 I Digital 1.8-V power supply
GND PowerPAD™ I Ground, 0 V
INAM 11 I Negative differential analog input for channel A
INAP 10 I Positive differential analog input for channel A
INBM 26 I Negative differential analog input for channel B
INBP 27 I Positive differential analog input for channel B
NC 2, 6, 7, 30, 31, 35, 37, 38, 40, 41 — Do not connect
OVRA 1 O Overrange indicator for channel A
OVRB 36 O Overrange indicator for channel B
PDN 33 I Power-down control. This pin has an internal 150-kΩ pulldown resistor.
RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.
SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.
SDATA 14 I Serial Interface data input. This pin has an internal 150-kΩ pulldown resistor.
SDOUT 16 O Serial interface data output
SEN 15 I Serial interface enable; active low.
This pin has an internal 150-kΩ pullup resistor to AVDD.
SYNCM~ 42 I Positive JESD204B synch input
SYNCP~ 43 I Negative JESD204B synch input
SYSREFM 23 I Negative external SYSREF input
SYSREFP 22 I Positive external SYSREF input
VCM 24 O Common-mode voltage output for analog inputs