JAJSOU1B june   2022  – august 2023 ADC32RF54 , ADC32RF55

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
    9. 6.9  Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
    10. 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics - ADC32RF54
    13. 6.13 Typical Characteristics - ADC32RF55
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping Using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDIO pins
          3. 7.3.5.7.3 Fast Frequency Hopping Using the Fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
        7. 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration Using the SPI Interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.1 Detailed Register Description

Figure 7-48 Register 0x00
76543210
0000000RESET
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-54 Register 0x00 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0RESETR/W0This bit resets all internal registers to the default values. Does not self clear to 0.
Figure 7-49 Register 0x05
76543210
MEM PAGEANALOG PAGECALIB PAGEDDCB PAGEDDCA PAGEJESD PAGEDIGITAL PAGE0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-55 Register 0x05 Field Descriptions
BitFieldTypeResetDescription
7MEM PAGER/W0This bit enables access to the MEMORY page
0: MEMORY page access disabled
1: MEMORY page access enabled
6ANALOG PAGER/W0This bit enables access to the ANALOG page
0: ANALOG page access disabled
1: ANALOG page access enabled
5CALIB PAGER/W0This bit enables access to the CALIBRATION page
0: CALIBRATION page access disabled
1: CALIBRATION page access enabled
4DDCB PAGER/W0This bit enables access to the DDCB page. Contents can be written to DDCA and DDCB page simultaneously if it is identical.
0: DDCB page access disabled
1: DDCB page access enabled.
3DDCA PAGER/W0This bit enables access to the DDCA page. Contents can be written to DDCA and DDCB page simultaneously if it is identical.
0: DDCA page access disabled
1: DDCA page access enabled
2JESD PAGER/W0This bit enables access to the JESD page
0: JESD page access disabled
1: JESD page access enabled
1DIGITAL PAGER/W0This bit enables access to the DIGITAL page
0: DIGITAL page access disabled
1: DIGITAL page access enabled
00R/W0Must write 0
Figure 7-50 Register 0x2C (DIGITAL page)
76543210
20-BIT OUTDDC BAND SEL000DDC REALBYP EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-56 Register 0x2C Field Descriptions
BitFieldTypeResetDescription
720-BIT OUTR/W0This bit enables the 20-bit output mode. It carries the output sample with 20-bit output resolution from the DDC and the sample is filled to 32-bit with 12 trailing 0s.
0: Normal operation
1: 20-bit output mode
6-5DDC BAND SELR/W00Selects 1, 2 or 4 DDC per ADC when complex decimation is enabled
0: Single band
1: Dual band
2: Quad band
3: not used
4-20R0Must write 0
1DDC REALR/W0This bit enables real decimation filter (NCO = 0). BYP EN (D0) must be set to 0.
0: Complex decimation
1: Real decimation
0BYP ENR/W0This bit enables DDC bypass mode
0: Decimation filter enabled. Complex decimation by default unless D1 is set
1: Decimation filter bypass
Figure 7-51 Register 0x2D (DIGITAL page)
76543210
0DECIMATION0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-57 Register 0x2D Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-4DECIMATIONR/W0Selects decimation.
0,1: not used
2: Decimation by 4
3: Decimation by 8
4: Decimation by 16
5: Decimation by 32
6: Decimation by 64
7: Decimation by 128
3-00R/W0Must write 0
Figure 7-52 Register 0x2E (DIGITAL page)
76543210
0000AVG ENAVG SEL (1)OVR ON JESD
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-58 Register 0x2E Field Descriptions
BitFieldTypeResetDescription
7-40R/W0Must write 0
3AVG ENR/W0This bit enables averaging
0: no average
1: ADC averaging enabled
2-1AVG SEL (1)R/W00Selects ADC averaging. Also AVG SEL (2) in CALIBRATION page needs to be set.
0: no average
1: 2 ADC average
2: 4 ADC average
0OVR ON JESDR/W0This bit enables to output OVR flag to replace the LSB in the JESD output stream
0: OVR on GPIO
1: OVR replaces LSB on JESD stream
Figure 7-53 Register 0x33 (DIGITAL page)
76543210
0001FORMAT0GBL PDN0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-59 Register 0x33 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
41R/W0Must write 1
3FORMATR/W0This register bit determines the output data format in DDC bypass mode only.
0: Offset Binary
1: 2s Complement
DDC mode only supports 2s complement output format.
20R/W0Must write 0
1GBL PDNR/W0This register bit enables global power down mode
0: normal operation
1: global power down mode enabled
00R/W0Must write 0
Figure 7-54 Register 0x34 (DIGITAL page)
76543210
0MEM STROBEMEM CH SEL0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-60 Register 0x34 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6MEM STROBER/W0This register enables fast power down mode
0: normal operation
1: fast power down mode enabled
5-4MEM CH SELR/W0This register selects which ADC channel is used to fill up the capture sample buffer. Only 1 channel can be selected at a time and the samples are captured from the ADC core without averaging or decimation.
00: capture memory is filled from chA1 input
01: capture memory is filled from chA2 input
10: capture memory is filled from chB1 input
11: capture memory is filled from chB2 input
00R/W0Must write 0
Figure 7-55 Register 0x3B (DIGITAL page)
76543210
NCO4 CHA [1:0]NCO3 CHA [1:0]NCO2 CHA [1:0]NCO1 CHA [1:0]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-61 Register 0x3B Field Descriptions
BitFieldTypeResetDescription
7-6NCO4 CHA [1:0]R/W00This register is used when selecting the NCO frequency for channel A, band 4 with the SPI interface in quad DDC mode.
5-4NCO3 CHA [1:0]R/W00This register is used when selecting the NCO frequency for channel A, band 3 with the SPI interface in quad DDC mode.
3-2NCO2 CHA [1:0]R/W00In single band DDC mode this register is used to select between NCO bank 1 or 2.
00: NCO bank 1
01: NCO bank 2
In dual band DDC mode this register is used to select the NCO frequency for channel A, band 2 with the SPI interface.
1-0NCO1 CHA [1:0]R/W00This register is used when selecting the NCO1 of channel A with the SPI interface.
Figure 7-56 Register 0x41 (DIGITAL page)
76543210
NCO4 CHB [1:0]NCO3 CHB [1:0]NCO2 CHB [1:0]NCO1 CHB [1:0]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-62 Register 0x41 Field Descriptions
BitFieldTypeResetDescription
7-6NCO4 CHB [1:0]R/W00This register is used when selecting the NCO frequency for channel B, band 4 with the SPI interface in quad DDC mode.
5-4NCO3 CHB [1:0]R/W00This register is used when selecting the NCO frequency for channel B, band 3 with the SPI interface in quad DDC mode.
3-2NCO2 CHB [1:0]R/W00In single band DDC mode this register is used to select between NCO bank 1 or 2 of channel B.
00: NCO bank 1
01: NCO bank 2
In dual band DDC mode this register is used to select the NCO frequency for channel B, band 2 with the SPI interface.
1-0NCO1 CHB [1:0]R/W00This register is used when selecting the NCO1 of channel B with the SPI interface.
Figure 7-57 Register 0x22F (DIGITAL page)
76543210
1SYSREF X5SYSREF X4SYSREF X3SYSREF X2SYSREF X1SYSREF OR1
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-63 Register 0x22F Field Descriptions
BitFieldTypeResetDescription
71R/W1Must write 1
6-2SYSREF X1..5R/W0These bits are the XOR flags from the SYSREF window monitoring circuitry. The sampling clock gets delayed internally by ~ 160 ps and used to capture the SYSREF signal. If a SYSREF signal transition happens within +/- 50 ps of the SYSREF capture the appropriate XOR flag gets raised. These bits are not sticky - they get overwritten with the next SYSREF rising edge.
X1: Window from 110 ps to 135 ps after the rising sampling clock edge
X2: Window from 135 ps to 160 ps after the rising sampling clock edge
X3: Window from 160 ps to 176 ps after the rising sampling clock edge
X4: Window from 176 ps to 192 ps after the rising sampling clock edge
X5: Window from 192 ps to 208 ps after the rising sampling clock edge
0: No SYSREF transition detected
1: SYSREF transition detected within given window
1SYSREF ORR/W0This bit is the output of the five SYSREF XOR flags logically OR'ed together.
0: no SYSREF flag raised
1: one of the five SYSREF XOR flags is raised.
01R/W1Must write 1
Figure 7-58 Register 0x234 (DIGITAL page)
76543210
0NCO SEL MODE00GPIO MODE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-64 Register 0x234 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-5NCO SEL MODER/W00These bits select control of the NCO selection in complex decimation.
0: NCO selection using GPIO pins (GPIO MODE (D2-D0) needs to be set accordingly)
2: GPIO1/2 pins are used as a fast serial interface only for the NCO selection for each digital mixer
3: GPIO1/2, SCLK, SDIO pins are used for NCO selection.
others: not used
Register 0x235 may need to be set as well.
4-30R/W0Must write 0
2-0GPIO MODER/W000This register sets the functionality of the two GPIO pins
0: GPIO pins are used as SYNC input (LVDS), GPIO1 = SYNCP, GPIO2 = SYNCM
1: GPIO1 is used as SYNC input (CMOS)
3: Both GPIO pins are used to select NCOs for the decimation filters
4: GPIO1 is used to disable the calibration
5: GPIO1 is used as start of SYSREF counter
others: not used
Figure 7-59 Register 0x235 (DIGITAL page)
76543210
NCO SEL SOURCE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-65 Register 0x235 Field Descriptions
BitFieldTypeResetDescription
7-0NCO SEL SOURCER/W0This register works in conjuction with NCO SEL MODE (0x234).
0x00: NCO selection other than regular SPI (GPIO, Fast SPI etc)
0xFF: NCO selection using regular SPI with addresses 0x3B/41.
Figure 7-60 Register 0x236 (DIGITAL page)
76543210
0GPIO2 INVGPIO1 INVGPIO SWAP00SYSREF RESETSYSREF EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-66 Register 0x236 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6GPIO2 INVR/W0This bit inverts polarity of the GPIO2 pin
0: Polarity as is
1: Polarity inverted
5GPIO1 INVR/W0This bit inverts polarity of the GPIO1 pin
0: Polarity as is
1: Polarity inverted
4GPIO SWAPR/W0This bit swaps GPIO1 and GPIO2 pins internally.
0: Normal operation
1: GPIO1 and GPIO2 are swapped
3-20R/W0Must write 0
1SYSREF RESETR/W0This bit enables and clears the internal SYSREF counter:
0: Normal operation
1: Enables SYSREF and clears the internal counter
0SYSREF ENR/W0This bit starts the internal SYSREF counter:
0: Normal operation
1: Starts SYSREF counter
Figure 7-61 Register 0x237 (DIGITAL page)
76543210
00000GPIO2 CFG0GPIO1 CFG
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-67 Register 0x237 Field Descriptions
BitFieldTypeResetDescription
7-30R/W0Must write 0
2GPIO2 CFGR/W0This bit configures GPIO2 pin either as input or output.
0: GPIO2 pin is input
1: GPIO2 pin is output
10R/W0Must write 0
0GPIO1 CFGR/W0This bit configures GPIO1 pin either as input or output.
0: GPIO1 pin is input
1: GPIO1 pin is output
Figure 7-62 Register 0x238 (DIGITAL page)
76543210
OVR OUTPUT CFG0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-68 Register 0x238 Field Descriptions
BitFieldTypeResetDescription
7-4OVR OUTPUT CFGR/W0000This bit configures if the overrange indication (OVR) is output on JESD output stream or on GPIO pins
0000: OVR on JESD
1111: OVR on GPIO
3-00R/W0Must write 0
Figure 7-63 Register 0x20 (JESD page)
76543210
K
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-69 Register 0x20 Field Descriptions
BitFieldTypeResetDescription
7-0KR/W00000000This is JESD204B parameter K which sets number of frames in a multi-frame. Bit value is set as K minus 1.
Figure 7-64 Register 0x21 (JESD page)
76543210
0SYNC SPI ENSYNC SPI00SYSREF MODE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-70 Register 0x21 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6SYNC SPI ENR/W0This bit enables JESD SYNC control using SPI (ignoring SYNC using GPIO1/2 pins) using bit D5 (SYNC SPI).
0: SPI SYNC disabled
1: SPI SYNC (using register bit D5) enabled
5SYNC SPIR/W0This bit enables JESD SYNC. SYNC control via SPI must be enabled also (D6).
0: ADC outputs data (SYNC disabled)
1: SYNC enabled (ADC outputs K28.5 characters for JESD interface synchronization)
4-30R/W0Must write 0
2-0SYSREF MODER/W000This register controls how the ADC processes incoming SYSREF pulses.
0: Ignore all SYSREF pulses
1: Use all SYSREF pulses
2: Don't use SYSREF pulses
3: Skip one SYSREF pulse then use only the next one
4: Skip one SYSREF pulse then use all pulses
5: Skip two SYSREF pulses and then use one
6: Skip two SYSREF pulses and then use all
Figure 7-65 Register 0x22 (JESD page)
76543210
JESD MODE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-71 Register 0x22 Field Descriptions
BitFieldTypeResetDescription
7:0JESD MODER/W00000000This register sets the LMFS configuration
0: LMFS = 8-2-8-20 (also bit DROP LSB in 0x27 needs to be set)
1: LMFS = 8-2-2-4
3: LMFS = 8-4-2-2
4: LMFS = 8-16-4-1
5: LMFS = 4-16-8-1
6: LMFS = 2-16-16-1
7: LMFS = 1-16-32-1
8: LMFS = 8-8-2-1
9: LMFS = 4-8-4-1
10: LMFS = 2-8-8-1
11: LMFS = 1-8-16-1
12: LMFS = 4-4-2-1
13: LMFS = 2-4-4-1
14: LMFS = 1-4-8-1
15: LMFS = 2-2-2-1
16: LMFS = 1-2-4-1
others: not used
Figure 7-66 Register 0x24 (JESD page)
76543210
DDC CLK DIV
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-72 Register 0x24 Field Descriptions
BitFieldTypeResetDescription
7-0DDC CLK DIVR/W00000000This register sets the internal clock divider when using the decimation filter. See Table 7-74.
Figure 7-67 Register 0x25 (JESD page)
76543210
JESD TX CLK DIV
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-73 Register 0x25 Field Descriptions
BitFieldTypeResetDescription
7-0JESD TX CLK DIVR/W0000000This register sets the internal clock divider for the selected LMFS output mode. See Table 7-74 for 16-bit and Table 7-75 for 20-bit output.
Table 7-74 Register Settings for 0x24/0x25 Based on Bypass/Decimation and LMFS Mode (16-bit Output)
0x24 (DDC CLK DIV)0x25 (JESD TX CLK DIV)
LMFSBYP/4/8/16/32/64/128BYP/4/8/16/32/64/128
8-2-2-400
8-2-8-2004
8-4-8-1014
8-4-2-21000001111
8-8-2-10000000000
8-16-4-1111111000000
4-2-2-2000000111111
4-4-2-10000000000
4-8-4-1111111000000
4-16-8-1333333000000
2-2-2-10000000000
2-4-4-1111111000000
2-8-8-1333333000000
2-16-16-17777700000
1-2-4-1111111000000
1-4-8-1333333000000
1-8-16-17777700000
1-16-32-1151515150000
Table 7-75 Register Settings for 0x24/0x25 Based on Decimation and LMFS Mode (20-bit Output).
0x24 (DDC CLK DIV)0x25 (JESD TX CLK DIV)
LMFSBYP/4/8/16/32/64/128BYP/4/8/16/32/64/128
8-8-4-1111111000000
8-16-8-1333333000000
4-4-4-1111111000000
4-8-8-1333333000000
4-16-16-17777700000
2-2-4-1111111000000
2-4-8-1333333000000
2-8-16-17777700000
2-16-32-1151515150000
1-2-8-1333333000000
1-4-16-17777700000
1-8-32-1151515150000
1-16-64-1313131000
Figure 7-68 Register 0x27 (JESD page)
76543210
00DROP LSB000CLK BAL EN0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-76 Register 0x27 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5DROP LSBR/W0This register needs to be set when using the 12-bit output LMFS mode.
0: Drop LSB disabled
1: Drop LSB enabled when using LMFS = 8-2-8-2-20
4-20R/W0Must write 0
1CLK BAL ENR/W0This register bit needs to be enabled in bypass mode LMFS = 8-2-2-4 only in order to improve some internal clock balancing.
0: CLK BAL disabled
1: CLK BAL EN. Set for LMFS = 8-2-2-4
00R/W0Must write 0
Figure 7-69 Register 0x28 (JESD page)
76543210
JESD LANE EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-77 Register 0x28 Field Descriptions
BitFieldTypeResetDescription
7-0JESD LANE ENR/W11111111This register turns on individual output lanes
0: Lane powered down
1: Serdes lane enabled
D0: Lane DOUT0
D1: Lane DOUT1
...
D7: Lane DOUT7
Figure 7-70 Register 0x2B
76543210
0000000SYNC INV
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-78 Register 0x2B Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0SYNC INVR/W0This register inverts the polarity from external SYNC pin
0: Polarity as is
1: Polarity inverted
Figure 7-71 Register 0x2D (JESD page)
76543210
00000JESD SEQ SEL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-79 Register 0x2D Field Descriptions
BitFieldTypeResetDescription
7-30R/W0Must write 0
2-0JESD SEQ SELR/W000This register selects the JESD test pattern sequence
0: Test sequence disabled
1: Repeat D21.5 high frequency pattern for random jitter (RJ)
2: Repeat K28.5 mixed frequency pattern for deterministic jitter (DJ)
3: Repeat initial lane alignment (ILA) sequence
4: Modified random pattern
5: Scrambled jitter pattern
6: Repeat K28.7 low frequency pattern
7: Short test pattern
Figure 7-72 Register 0x2E (JESD page)
76543210
RAMP INCR0RAMP ENALT PAT0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-80 Register 0x2E Field Descriptions
BitFieldTypeResetDescription
7-4RAMP INCRR/W0000This register value sets the increment step size for the ramp pattern on 16-bit output. The step size is RAMP INCR plus 1.
30R/W0Must write 0
2RAMP ENR/W0Enables RAMP output pattern in the TRANSPORT LAYER.
1ALT PATR/W0Enables a toggle pattern switching between 0x0000 and 0xFFFF in the TRANSPORT LAYER
00R/W0Must write 0
Figure 7-73 Register 0x2F (JESD page)
76543210
0SERDES PRBSSERDES PRBS EN0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-81 Register 0x2F Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-5SERDES PRBSR/W0This register selects the PRBS pattern in the LINK LAYER (no 8b/10b encoding). PRBS pattern must be enabled (D4).
0: PRBS 27-1
1: PRBS 215-1
2: PRBS 223-1
3: PRBS 231-1
4SERDES PRBS ENR/W0This register enables PRBS test pattern in the LINK LAYER
0: Test pattern mode disabled
1: PRBS test pattern mode enabled
3-00R/W0Must write 0
Figure 7-74 Register 0x30/32/34/36/40/42/44/46 (JESD page)
76543210
START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-82 Register 0x30/32/34/36/40/42/44/46 Field Descriptions
BitFieldTypeResetDescription
7-0START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7R/W00000000The JESD RAMP test pattern is designed to act as an individual RAMP pattern on each output lane. If the starting value on each lane is set to 0 (default), each output lane shows the same RAMP code at any given time.
The RAMP pattern can be configured such that the RAMP pattern is constructed across JESD output lanes using the start value registers.
DOUT1=1, DOUT2=2, DOUT3=3, DOUT4=0, DOUT5=1, DOUT6=2 and DOUT7=3 as well as the RAMP increment to 4 (RAMP INCR (0x2E) = 0x30) results in a RAMP pattern across lanes for each channel in bypass mode.
Figure 7-75 Register 0x53 (JESD page)
76543210
SCR EN0000000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-83 Register 0x53 Field Descriptions
BitFieldTypeResetDescription
7SCR ENR/W0Enables scrambling of the JESD output data
0: Output scrambling disabled
1: Output scrambling enabled
6-00R/W0Must write 0
Figure 7-76 Register 0x7A (JESD page)
76543210
JESD LANE POL INV
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-84 Register 0x7A Field Descriptions
BitFieldTypeResetDescription
7-0JESD LANE POL INVR/W00000000This register inverts the polarity of the individual SERDES output lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1 to DOUT1 etc
0: Output polarity as is
1: Output polarity inverted
Figure 7-77 Register 0x80/81/82/83 (JESD page)
ADDR76543210
0x800LANE DOUT1 SEL0LANE DOUT0 SEL
0x810LANE DOUT3 SEL0LANE DOUT2 SEL
0x820LANE DOUT5 SEL0LANE DOUT4 SEL
0x830LANE DOUT7 SEL0LANE DOUT6 SEL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-85 Register 0x80/81/82/83 Field Descriptions
BitFieldTypeResetDescription
7,30R/W0Must write 0
6-4LANE DOUT1/3/5/7 SELR/W000These register bits control the output mux. Any physical serdes output lane (DOUTx) can be connected to any JESD digital stream. By default lane DOUT0 is connected to JESD stream 0, lane DOUT1 to JESD stream 1 etc.
0: JESD stream 0
1: JESD stream 1
...
7: JESD stream 7
2-0LANE DOUT0/2/4/6 SELR/W000
Figure 7-78 Register 0x84 (JESD page)
76543210
000000JESD PLL FACTOR
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-86 Register 0x84 Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1-0JESD PLL FACTORR/W00This register bit must be set for 12-bit output LMFS = 8-2-8-20 only.
0: all other JESD LMFS modes
1: Set for LMFS = 8-2-8-20
Figure 7-79 Register 0x89/8A/8B/8C/8D/8E/8F/90 (JESD page)
ADDR76543210
0x89TX EMPH DOUT1 [0]TX EMPH DOUT0 [5:0]0
0x8A000TX EMPH DOUT1 [5:1]
0x8BTX EMPH DOUT3 [0]TX EMPH DOUT2 [5:0]0
0x8C000TX EMPH DOUT3 [5:1]
0x8DTX EMPH DOUT5 [0]TX EMPH DOUT4 [5:0]0
0x8E000TX EMPH DOUT5 [5:1]
0x8FTX EMPH DOUT7 [0]TX EMPH DOUT6 [5:0]0
0x90000TX EMPH DOUT7 [5:1]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-87 Register 0x89/8A/8B/8C/8D/8E/8F/90 Field Descriptions
BitFieldTypeResetDescription
7-5,00R/W0Must write 0
6-1TX EMPH DOUT0/2/4/6 [5:0]R/W000000These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period.
0: 0 dB
1: –1 dB
3: –2 dB
7: –4.1 dB
15: –6.2 dB
31: –8.2 dB
63: –11.5 dB
4-0,7TX EMPH DOUT1/3/5/7 [5:0]R/W000000
Figure 7-80 Register 0x9D/9E (JESD page)
76543210
PD DOUT7 [0,1]PD DOUT6 [0,1]PD DOUT5 [0,1]PD DOUT4 [0,1]PD DOUT3 [0,1]PD DOUT2 [0,1]PD DOUT1 [0,1]PD DOUT0 [0,1]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-88 Register 0x9D/9E Field Descriptions
BitFieldTypeResetDescription
7-0PD DOUTx [0,1]R/W0Register 0x9D and 0x9E allow power down of individual serdes output lanes. Register 0x9D (PD DOUTx [0]) covers the output driver, 0x9E (PD DOUTx [1]) covers the associated internal high-speed data clock.
0: Output lane enabled
1: Output lane powered down
Figure 7-81 Register 0x9F (JESD page)
76543210
0JESD PLL10JESD PLL2
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-89 Register 0x9F Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-4JESD PLL1R/W000Internal JESD PLL input divider setting. See Table 7-91 how to configure it for the different decimation and LMFS settings.
30R/W0Must write 0
2-0JESD PLL2R/W000Internal JESD PLL input divider setting. See Table 7-91 how to configure it for the different decimation and LMFS settings.
Figure 7-82 Register 0xA0/A1/A2 (JESD page)
ADDR76543210
0xA00JESD PLL INPUT10000
0xA10JESD PLL INPUT20000
0xA20000JESD PLL INPUT30
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-90 Register 0xA0/A1/A2 Field Descriptions
BitFieldTypeResetDescription
7-00R/W0Must write 0
6-4JESD PLL INPUT1/2R/W000Internal JESD PLL input divider setting. See Table 7-91 (16-bit output) and Table 7-91 (20-bit output) how to configure it for the different decimation and LMFS settings.
3-1JESD PLL INPUT3R/W000Internal JESD PLL input divider setting. See Table 7-91 (16-bit output) and Table 7-91 (20-bit output)how to configure it for the different decimation and LMFS settings.
Table 7-91 Register settings for 0x9F/A0/A1/A2 based on bypass/decimation and LMFS mode (16-bit output)
JESD PLL1/2, JESD PLL INPUT 1/2 JESD PLL INPUT 3
LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128
8-2-2-4 0 0
8-2-8-20 0 0
8-4-8-10 0 1
8-4-2-2 0 1 2 3 3 1 0 0 0 2
8-8-2-1 0 1 2 3 4 0 0 0 0 0
8-16-4-1 0 0 1 2 3 4 1 0 0 0 0 0
4-2-2-2 1 2 3 0 0 0
4-4-2-1 0 1 2 3 4 0 0 0 0 0
4-8-4-1 0 0 1 2 3 4 1 0 0 0 0 0
4-16-8-1 0 0 0 1 2 3 3 1 0 0 0 0
2-2-2-1 0 1 2 3 4 0 0 0 0 0
2-4-4-1 0 0 1 2 3 4 0 0 0 0 0 0
2-8-8-1 0 0 0 1 2 3 3 1 0 0 0 0
2-16-16-1 0 0 0 1 2 3 1 0 0 0
1-2-4-1 0 0 1 2 3 4 1 0 0 0 0 0
1-4-8-1 0 0 0 1 2 3 3 1 0 0 0 0
1-8-16-1 0 0 0 1 2 3 1 0 0 0
1-16-32-1 0 0 0 1 3 1 0 0
Table 7-92 Register settings for 0x9F/A0/A1/A2 based on decimation and LMFS mode (20-bit output)
JESD PLL1/2, JESD PLL INPUT 1/2 JESD PLL INPUT 3
LMFS /4 /8 /16 /32 /64 /128 /4 /8 /16 /32 /64 /128
8-8-4-1 0 0 1 2 3 4 1 0 0 0 0 0
8-16-8-1 0 0 0 1 2 3 3 1 0 0 0 0
4-4-4-1 0 0 1 2 3 4 1 0 0 0 0 0
4-8-8-1 0 0 0 1 2 3 3 1 0 0 0 0
4-16-16-1 0 0 0 1 2 3 1 0 0 0
2-2-4-1 0 0 1 2 3 4 1 0 0 0 0 0
2-4-8-1 0 0 0 1 2 3 3 1 0 0 0 0
2-8-16-1 0 0 0 1 2 3 1 0 0 0
2-16-32-1 0 0 0 1 3 1 0 0
1-2-8-1 0 0 0 1 2 3 3 1 0 0 0 0
1-4-16-1 0 0 0 1 2 3 1 0 0 0
1-8-32-1 0 0 0 1 3 1 0 0
1-16-64-1 0 0 0 3 1 0
Figure 7-83 Register 0x100..0x17D (DDCA/B page)
76543210
NCOx FREQUENCYx [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-93 Register 0x100..0x17D Field Descriptions
BitFieldTypeResetDescription
47:0NCOx FREQUENCYxR/W0The frequencies for NCOs are located in addresses 0x100 to 0x17D. Each frequency is 48-bit and the MSB starts on the highest address as illustrated in Section 7.3.5.6.
Figure 7-84 Register 0x180 (DDCA/B page)
76543210
00DDC PDNDDC DITH PDNREAL DDCDB/QB DDC0NCO MODE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-94 Register 0x180 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5DDC PDNR/W0This bit powers down the DDC mixer and NCO
0: DDC block enabled
1: DDC block powered down
4DDC DITH PDNR/W0This bit powers down the dither in the DDC digital block
0: DDC dither enabled
1: DDC dither powered down
3REAL DDCR/W0Set this bit to 1 in real decimation mode to disable the NCO.
0: Complex Decimation
1: Real Decimation
2DB/QB DDCR/W0This register splits the NCOs for dual or quad band operation.
0: Dual Band
1: Quad Band
10R/W0Must write 0
0NCO MODER/W0This register selects phase coherent or phase continuous operation of the NCO.
0: Phase continuous
1: Phase coherent
Figure 7-85 Register 0x181 (DDCA/B page)
76543210
00LOAD NCO0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-95 Register 0x181 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5-4LOAD NCOR/W00This register loads all the NCO frequencies from the memory to the NCOs. To update the NCO this register has to be set to 3 and back to 0 as shown in Table 7-96.
3-00R/W0Must write 0
Table 7-96 NCO frequency programming example
ADDRDATADESCRIPTION
0x1050x4EFrequency = 920 MHz with FS = 3 GSPS
86,318,992,857,935 = 0x4E81B4E81BE4 where the MSB goes to address 0x105 and the LSB to 0x100.
0x1040x81
0x1030xB4
0x1020xE8
0x1010x1B
0x1000x4E
0x1810x00Load and update all NCO frequencies
0x1810x30
Figure 7-86 Register 0x34 (CALIBRATION page)
76543210
00000AVG SEL (2)1
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-97 Register 0x34 Field Descriptions
BitFieldTypeResetDescription
7-30R/W0Must write 0
2-1AVG SEL (2)R/W00Selects ADC averaging. Also AVG SEL (1) in DIGITAL page needs to be set.
0: no average
01: 2 ADC average
10: not used
11: 4 ADC average
01R/W1Must write 1
Figure 7-87 Register 0x45 (CALIBRATION page)
76543210
CAL SPICAL GPIO001010
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-98 Register 0x45 Field Descriptions
BitFieldTypeResetDescription
7CAL SPIR/W0This register triggers the calibration using SPI write. It needs to be toggled (0=>1=>0).
6CAL GPIOR/W0This register triggers the calibration using the GPIO1 pin.
5-40R/W0Must write 0
31R/W1Must write 1
20R/W0Must write 0
11R/W1Must write 1
00R/W0Must write 0
Figure 7-88 Register 0x298 (CALIBRATION page)
76543210
0000CAL STATUS
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-99 Register 0x298 Field Descriptions
BitFieldTypeResetDescription
7-40R/W0Must write 0
3-0CAL STATUSR/W0000

This register can be used to check if calibration state machine has finished without any errors. A value of 0xE indicates successful calibration.

Figure 7-89 Register 0x6D/6E (ANALOG page)
76543210
RESET SW [1:0]000000
000000RESET SW [3:2]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-100 Register 0x6D/6E Field Descriptions
BitFieldTypeResetDescription
7-6RESET SW [1:0]R/W00This register disables the sampling reset switch.
00: Sampling reset switch enabled
1: Sampling reset switch disabled
5-00R/W0Must write 0
1-0RESET SW [3:2]R/W00This register disables the sampling reset switch.
00: Sampling reset switch enabled
1: Sampling reset switch disabled
7-20R/W0Must write 0
Figure 7-90 Register 0x7B (ANALOG page)
76543210
00TERM A0000TERM A
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-101 Register 0x7B Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5,0TERM AR/W00These registers set the internal termination resistor at the analog inputs for channel A1 and A2. Both registers need to be set to the same value.
0: 100 ohm differential termination
1: 50 ohm differential termination
4-10R/W0Must write 0
Figure 7-91 Register 0x8B (ANALOG page)
76543210
00TERM B0000TERM B
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-102 Register 0x8B Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5,0TERM BR/W00These registers set the internal termination resistor at the analog inputs for channel B1 and B2. Both registers need to be set to the same value.
0: 100 ohm differential termination
1: 50 ohm differential termination
4-10R/W0Must write 0
Figure 7-92 Register 0xA8 (ANALOG page)
76543210
0DITH AMP1000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-103 Register 0xA8 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-3DITH AMP1R/W0000This register sets dither amplitude coarse gain. There are two recommended settings:
0000: Amplitude = 0
0011: Amplitude = 3
Here is a list of all the settings:
0000: Amplitude = 0 (smallest)
0001: Amplitude = 1
...
1110: Amplitude = 14
1111: Amplitude = 15 (largest)
2-00R/W0Must write 0
Figure 7-93 Register 0xAF (ANALOG page)
76543210
DITHER DIS0010000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-104 Register 0xAF Field Descriptions
BitFieldTypeResetDescription
7DITHER DISR/W0This register disables internal dither.
0: Dither enabled
1: Dither disabled
6-50R/W0Must write 0
41R/W0Must write 1
3-00R/W0Must write 0
Figure 7-94 Register 0xB1 (ANALOG page)
76543210
DITHER DIVIDER
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-105 Register 0xB1 Field Descriptions
BitFieldTypeResetDescription
7-0DITHER DIVIDERR/W0This register sets the dither divider frequency. SPI write is actual -1. For example a divider of 48 is 47 (0x2F).
0x00 (default) is a divide /50
Figure 7-95 Register 0xB4 (ANALOG page)
76543210
0000000SYSREF AC
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-106 Register 0xB4 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0SYSREF ACR/W0This register enables external AC coupling of the SYSREF input with internal biasing.
0: External DC coupling with internal 100 Ω termination
1: External AC coupling with internal biasing
Figure 7-96 Register 0xCD (ANALOG page)
76543210
0DITH AMP20000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-107 Register 0xCD Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-4DITH AMP2R/W0This register sets dither amplitude fine gain. There are two recommended settings:
000: Amplitude = 0
100: Amplitude = -4
Here is a list of all the settings:
000: Amplitude = 0
001: Amplitude = 1
010: Amplitude = 2
011: Amplitude = 3 (largest)
100: Amplitude = -4 (smallest)
101: Amplitude = -3
110: Amplitude = -2
111: Amplitude = -1
3-00R/W0Must write 0
Figure 7-97 Register 0xE6/E7 (ANALOG page)
ADDR76543210
0xE6TX SWING [0]0000000
0xE7000000TX SWING [2:1]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 7-108 Register 0xE6/E7 Field Descriptions
BitFieldTypeResetDescription
7-00R/W0Must write 0
1,0,7TX SWING [2:0]R/W000This register adjusts the output amplitude on all 8 serdes lanes.
0: 850 mVpp
1: 825 mVpp
2: 800 mVpp
3: 775 mVpp
4: 950 mVpp
5: 925 mVpp
6: 900 mVpp
7: 875 mVpp