JAJSCV8B May   2016  – December 2021 ADC32RF80 , ADC32RF83

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance Characteristics: fS = 2949.12 MSPS
    7. 6.7  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A + D Band)
    8. 6.8  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A Band)
    9. 6.9  Digital Requirements
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Input Clock Diagram
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
        1. 8.3.1.1 Input Clamp Circuit
      2. 8.3.2  Clock Input
      3. 8.3.3  SYSREF Input
        1. 8.3.3.1 Using SYSREF
        2. 8.3.3.2 Frequency of the SYSREF Signal
      4. 8.3.4  DDC Block
        1. 8.3.4.1 Operating Mode: Receiver
        2. 8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
        3. 8.3.4.3 Decimation Filters
          1. 8.3.4.3.1  Divide-by-4
          2. 8.3.4.3.2  Divide-by-6
          3. 8.3.4.3.3  Divide-by-8
          4. 8.3.4.3.4  Divide-by-9
          5. 8.3.4.3.5  Divide-by-10
          6. 8.3.4.3.6  Divide-by-12
          7. 8.3.4.3.7  Divide-by-16
          8. 8.3.4.3.8  Divide-by-18
          9. 8.3.4.3.9  Divide-by-20
          10. 8.3.4.3.10 Divide-by-24
          11. 8.3.4.3.11 Divide-by-32
          12. 8.3.4.3.12 Latency with Decimation Options
        4. 8.3.4.4 Digital Multiplexer (MUX)
        5. 8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 8.3.5  NCO Switching
      6. 8.3.6  SerDes Transmitter Interface
      7. 8.3.7  Eye Diagrams
      8. 8.3.8  Alarm Outputs: Power Detectors for AGC Support
        1. 8.3.8.1 Absolute Peak Power Detector
        2. 8.3.8.2 Crossing Detector
        3. 8.3.8.3 RMS Power Detector
        4. 8.3.8.4 GPIO AGC MUX
      9. 8.3.9  Power-Down Mode
      10. 8.3.10 ADC Test Pattern
        1. 8.3.10.1 Digital Block
        2. 8.3.10.2 Transport Layer
        3. 8.3.10.3 Link Layer
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Frame Assembly
        3. 8.4.2.3 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        4. 8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 8.4.2.6 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        7. 8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 8.4.3 Serial Interface
        1. 8.4.3.1 Serial Register Write: Analog Bank
        2. 8.4.3.2 Serial Register Readout: Analog Bank
        3. 8.4.3.3 Serial Register Write: Digital Bank
        4. 8.4.3.4 Serial Register Readout: Digital Bank
        5. 8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
    5. 8.5 Register Maps
      1. 8.5.1  Example Register Writes
      2. 8.5.2  Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 000h (address = 000h), General Registers
          2. 8.5.2.1.2 Register 002h (address = 002h), General Registers
          3. 8.5.2.1.3 Register 003h (address = 003h), General Registers
          4. 8.5.2.1.4 Register 004h (address = 004h), General Registers
          5. 8.5.2.1.5 Register 010h (address = 010h), General Registers
          6. 8.5.2.1.6 Register 011h (address = 011h), General Registers
          7. 8.5.2.1.7 Register 012h (address = 012h), General Registers
      3. 8.5.3  Master Page (M = 0)
        1. 8.5.3.1 Register 020h (address = 020h), Master Page
        2. 8.5.3.2 Register 032h (address = 032h), Master Page
        3. 8.5.3.3 Register 039h (address = 039h), Master Page
        4. 8.5.3.4 Register 03Ch (address = 03Ch), Master Page
        5. 8.5.3.5 Register 05Ah (address = 05Ah), Master Page
        6. 8.5.3.6 Register 03Dh (address = 3Dh), Master Page
        7. 8.5.3.7 Register 057h (address = 057h), Master Page
        8. 8.5.3.8 Register 058h (address = 058h), Master Page
      4. 8.5.4  ADC Page (FFh, M = 0)
        1. 8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
        2. 8.5.4.2 Register 042h (address = 042h), ADC Page
      5. 8.5.5  Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
        1. 8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
      6. 8.5.6  Offset Corr Page Channel A (610000h, M = 1)
        1. 8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
        2. 8.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
      7. 8.5.7  Offset Corr Page Channel B (610000h, M = 1)
        1. 8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
      8. 8.5.8  Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
      9. 8.5.9  Main Digital Page Channel A (680000h, M = 1)
        1. 8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
        2. 8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
      10. 8.5.10 Main Digital Page Channel B (680001h, M = 1)
        1. 8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
        2. 8.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
      11. 8.5.11 JESD Digital Page (6900h, M = 1)
        1. 8.5.11.1  Register 001h (address = 001h), JESD Digital Page
        2. 8.5.11.2  Register 002h (address = 002h ), JESD Digital Page
        3. 8.5.11.3  Register 003h (address = 003h), JESD Digital Page
        4. 8.5.11.4  Register 004h (address = 004h), JESD Digital Page
        5. 8.5.11.5  Register 006h (address = 006h), JESD Digital Page
        6. 8.5.11.6  Register 007h (address = 007h), JESD Digital Page
        7. 8.5.11.7  Register 016h (address = 016h), JESD Digital Page
        8. 8.5.11.8  Register 017h (address = 017h), JESD Digital Page
        9. 8.5.11.9  Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 8.5.11.10 Register 036h (address = 036h), JESD Digital Page
        11. 8.5.11.11 Register 037h (address = 037h), JESD Digital Page
        12. 8.5.11.12 Register 03Ch (address = 03Ch), JESD Digital Page
        13. 8.5.11.13 Register 03Eh (address = 03Eh), JESD Digital Page
      12. 8.5.12 Decimation Filter Page
        1. 8.5.12.1  Register 000h (address = 000h), Decimation Filter Page
        2. 8.5.12.2  Register 001h (address = 001h), Decimation Filter Page
        3. 8.5.12.3  Register 002h (address = 2h), Decimation Filter Page
        4. 8.5.12.4  Register 005h (address = 005h), Decimation Filter Page
        5. 8.5.12.5  Register 006h (address = 006h), Decimation Filter Page
        6. 8.5.12.6  Register 007h (address = 007h), Decimation Filter Page
        7. 8.5.12.7  Register 008h (address = 008h), Decimation Filter Page
        8. 8.5.12.8  Register 009h (address = 009h), Decimation Filter Page
        9. 8.5.12.9  Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 8.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 8.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 8.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 8.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 8.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 8.5.12.15 Register 010h (address = 010h), Decimation Filter Page
        16. 8.5.12.16 Register 011h (address = 011h), Decimation Filter Page
        17. 8.5.12.17 Register 014h (address = 014h), Decimation Filter Page
        18. 8.5.12.18 Register 016h (address = 016h), Decimation Filter Page
        19. 8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
        22. 8.5.12.22 Register 037h (address = 037h), Decimation Filter Page
          1. 8.5.12.22.1 Register 038h (address = 038h), Decimation Filter Page
          2. 8.5.12.22.2 Register 039h (address = 039h), Decimation Filter Page
        23. 8.5.12.23 Register 03Ah (address = 03Ah), Decimation Filter Page
      13. 8.5.13 Power Detector Page
        1. 8.5.13.1  Register 000h (address = 000h), Power Detector Page
        2. 8.5.13.2  Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 8.5.13.3  Register 003h (address = 003h), Power Detector Page
        4. 8.5.13.4  Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 8.5.13.5  Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 8.5.13.6  Register 00Dh (address = 00Dh), Power Detector Page
        7. 8.5.13.7  Register 00Eh (address = 00Eh), Power Detector Page
        8. 8.5.13.8  Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 8.5.13.9  Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 8.5.13.11 Register 020h (address = 020h), Power Detector Page
        12. 8.5.13.12 Register 021h (address = 021h), Power Detector Page
        13. 8.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 8.5.13.14 Register 027h (address = 027h), Power Detector Page
        15. 8.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
        16. 8.5.13.16 Register 032h-035h (address = 032h-035h), Power Detector Page
        17. 8.5.13.17 Register 037h (address = 037h), Power Detector Page
        18. 8.5.13.18 Register 038h (address = 038h), Power Detector Page
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
        1. 9.1.3.1 External Clock Phase Noise Consideration
      4. 9.1.4 Power Consumption in Different Modes
      5. 9.1.5 Using DC Coupling in the ADC32RF8x
        1. 9.1.5.1 Bypassing the Offset Corrector Block
          1. 9.1.5.1.1 Effect of Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER CONSUMPTION(4) (Dual-Channel Operation, Both Channels A and B are Active; Divide-by-4, Complex Output Mode(3))
IAVDD191.9-V analog supply currentfS = 2949.12 MSPS17771989mA
IAVDD1.15-V analog supply currentfS = 2949.12 MSPS9701103mA
IDVDD1.15-V digital supply currentfS = 2949.12 MSPS17851955mA
PDPower dissipationfS = 2949.12 MSPS6.547.07W
Global power-down power dissipation360mW
ANALOG INPUTS
Resolution14Bits
Differential input full-scale1.35VPP
VICInput common-mode voltage1.2(5)V
RINInput resistanceDifferential resistance at dc65Ω
CINInput capacitanceDifferential capacitance at dc2pF
VCM common-mode voltage output1.2V
Analog input bandwidth
(–3-dB point)		ADC driven with 50-Ω source3200MHz
ISOLATION
Crosstalk isolation between channel A and channel B(1)fIN = 100 MHz100dBc
fIN = 900 MHz99
fIN = 1800 MHz95
fIN = 2700 MHz86
fIN = 3500 MHz85
CLOCK INPUT(2)
Input clock frequency1.53GSPS
Differential (peak-to-peak) input clock amplitude0.51.52.5VPP
Input clock duty cycle45%50%55%
Internal clock biasing1.0V
Internal clock termination (differential)100Ω
(1) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.
(2) See Figure 7-1.
(3) Full-scale signal is applied to the analog inputs of all active channels.
(4) See the Section 9.1.4 section for more details.
(5) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance.