JAJSIB2 December 2019 ADC3421-Q1
PRODUCTION DATA.
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x serialization).